CA1182212A - Method and apparatus for recording digitized information on a record medium - Google Patents

Abstract

METHOD AND APPARATUS FOR RECORDING DIGITIZED
INFORMATION ON A RECORD MEDIUM

ABSTRACT OF THE DISCLOSURE

At least one channel of digitized information is recorded in at least one data track on a record medium by forming data blocks, each containing a predetermined number of data words representing the digitized information, and recording successive data blocks in at least one data track.
A block address also is generated to identify each of the respective data blocks, this block address also being recorded with the data block in the data track. A pre-determined number of successive data blocks is recorded in the data track in a sector interval. A control signal having at least a sector address for identifying the sector interval also is generated, and this control signal is recorded in a separate control track, successive control signals being recorded in successive sector intervals. The least significant bit of the sector address is coincident with the most significant bit of the block address, such that the block address is repeated with a periodicity related to the sector interval. The combination of the sector and block addresses is used to access a desired one of the recorded data blocks.

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Description

BACKGROUND OF THE X~VENTION
Thi~ invention relates to a me~hod and ~pparatus for recording channel~ of digi~ized informa~ion in data tracks on a record medium and, more par~icularly, ~ such ~ meth~d and appara~us wherein the digi~ized information i~ rcc~rded iD ~ucce~Biye data bl~cks in ak l ea~t one and, prefexably, in ~ plurality, of dat~ tr~cks, each recorded data block being separately accessible.
Digital r~cording technigue~ have been ext~nded to variouR fields in which analog recording heretofoxe had been used. ~or example, high quali~y audio recording now can be ~chieved by using digi~al ~echniques. So-called PCM recorder have been proposed or recording audio si~nals in digital form on a ~uitable magnetic record medium, ~uch as magnetic tape. U. S. Patent N~s. 4,211,997 and 4,145,683 describe two of these digital audio recording techniques.
Typically, digital ~ignals are recorded in various error-correction codes ~o as to prevent totBl 105s of infor-mation in the even~ of noise, interference, dropout, and other dis~urbance~ which may obliterate ~ portion of the.re-corded data. One xecent error correcting code which has been developed and which i6 particularly use~ul in recovering digitally encoded ~ignals that may be ~ubjected to ~uch obliteration is the so-called ~ros~-interleave error correction code described in, for example, U.S. Patent No~ 4,355,392 Issued October 19, 1982. Other error- _ _ correction encoding techniques also are known, such as described in Application Serial No. 361,558, filed October 3, 1980.

f'~i

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In such useful error correction codes, a number of digital words, each representiny, for example, a sample of an analog signal, are grouped in da~a blocks. Advantageously, and as described in the aforementioned applications, such data blocks are formed of time-interleaved digital words, together with time-interleaved parity words, the latter being used, upon reprodl1ction and time de-interleaving, to correct for errors that may be present in the digital words. The data blocks .in which the aforementioned time-1~ interleaved digital words are grouped are recorded in oneor more data tracks on the record medium.
When data blocks are recorded, as aforesaid, in a PCM audio recorder, a predetermined synchronizing signal may be inserted into every recorded data block, this synchronizing signal being used, during reproduction, by a servo system to control a tape-drive capstan such that the digital signals are reproduced with proper timing relationships. Such synchronizing signals thus are repro-duced with a period equal to the data block period.
'~ypically, such reproduced synchronizing signals exhibit a relatively high repetition rate, particularly if the length, or duration, of the data block is relatively short.
Such a short data block duration i5 advantageous in many error-correction decoding schemes. However, a relatively 2~ rapid repetition rate of this synchronizing signal which is used for carrying out a capstan servo operation places severe constraints on the tolerance o the servo system to account for jitter, timing errors due to expansion of the record medium, and the like.

PCM audio recorders offer the ad~antage that highly precise electronic editing may be performed.
For example, in a data track, a data block, which represents a relatively small increment of audio information, may be accessed, and that data block, as well as numerous succeeding data blocks, then may be modified, replaced, or the like~ The location at which this electronic editing commences is known as the "punch-in" point, and the location at which this editing terminates is known as the "punch-out" point. Of course, for optimum editing, the punch-in and punch-out points should be known with high accuracy. This can be achieved by identifying the particular data blocks which are located at the punch-in and punch-out points. Such data block identification, or access, may be obtained by providing a data block address at the beginning of each recorded data block. However, to avoid ambiguity, since a very large number of data blocks may be recorded in a data track, the data block address must be formed of a large number of bits. Consequently, the data block address may become unreasonably enlarged. For this reason, the use of a data bloc]c address at the beginning of each data block has not been enthusiastically adopted. Consequently, if a data block address is provided at the beginning of, 2S for example, a group of ten data blocks, thereby permitting the data block address to include a smallex number of bits, the punch-in and punch-out points cannot be selected with as great a precision as would otherwise obtain if the data block address is provided in each data block.

OBJECTS OF q~E INVENTION
Therefore, i$ is an object of the present invention to provide an improved method and apparatus for recording digitized information in the form of data blocks, which overcomes the aforenoted disadvantages and defects.
Another object of this invention i5 to provide an improved method and apparatus for recording at least one channel of digitized information in at leact one data track on a record medium, wherein the digitized info.rmation is recorded in individually identifiable and accessible data blocks.
A f~rther object of this invention is to provide an improved method and apparatus for recording digitized information, as aforesaid, wherein a synchronizing signal is recorded and subsequently reproduced for the purpose of servo control, the repetition rate of the r~produced synchronizing signal being sufficiently low in order to provide a greater range of tolerance for mechanical jitter, expansion of the record medium, and the like.
An additional object of this invention is to provide a method and apparatus for recording digitized information in at least one data track, wherein a separate control track also is recorded, the control track having a control signal recorded therein, which control signal includes at least a synchronizing signal which may be used~
upon reproduction, for servo control, and a sector address which is used to identify the digitized .information recoxded in the data tracks.
A still further object of this invention is to provide a method and apparatus for recording at least one channPl of digitized information in the form of data blocks in at least one data track on a record medium, each data block having a block address for identifying respective data blocks that are recorded in a sector interval, and wherein a control signal i~ xecorded on a separate control track, the control signal including the sector address for identifying successive sector intervals, each sector interval having a multiple of data blocks recorded therein, wherein the combination of the sector and block addresses i5 used to identify, or access, individual data blocks.
Various other objects, advantages and features of the present invention will become readily apparent from the ensuing detailed description, and the novel features will be particul&rly pointed out in the appended claims.
SUMMARY OF THE INVENTION
In accordance with this invention, a method and apparatus for rPcording at least one channel of digitized information in at least one data track on a record medium are provided. Stated in general terms, n channels of digitized information are recorded in m data tracks, wherein each channel is recorded in mn data tracks, with m ~n, and m and n are integers. The digitized information is encoded to for~ data blocks, each data block containing predetermined number of data words representing the digi-tized information, the data blocks being distributed to respective ones of the data tracks for recording therein.
Each data block also is provided with a block address which identifies that data block. Successive data blocks; includ-ing the respective block addresses, are recorded in each of the data tracksO A periodic control signal also is generated ~z~

during successive sector intervals, the periodic contr~l signal including at least a synchronizing siqnal and a sector address. The control signal is recorded in a control txack, each of the successive control signals being recorded in a respective sector inter~al. A multiple of data blocks is recorded in a given data track during each sector interval.
In accordance with one aspect of the present invention, the block address is comprised of a plurality of bits and the sector address is comprised of a larger number of bits, with the least significant bit of the sector address being coincident, i. e., being of the same logical sPnsel with the most significant bit of the block address.
In accordance with another aspect of this inven-tion, the respective block addresses are generated by incrementing the present block address for each data block to be recorded in a data track, with the block addresses being repeated after a predetermined number of sector intervals have been recorded. The sector addre,ss .is incremented for each control signal that is recorded, thereby providing substantially non-repeating sector addresses which may be recorded over the entire length of the record medium.
It is one feature of the present invention to record one channel of digitized information in plural data tracks by distributing the data blocks of that channel to such plural data trac~s, with each data track containing a multiple of data blocks during each sector interval. In 2~%

this arrangement, each data block that is recDrded in the same relative position in a ~ector interval in each o~f the plural data tr~cks exhlbits the 6ame block address.
A preerred u6e of the present invention i5 to record digitized audio Gisnals, ~uch a~ PCM audio ignals.
BRIEF DESCRIPTION OF l~ DR~WINGS
The following detailed description, given by way o example, will be~t be understood in conjunction with the accompanying drawings in which:
10' FIG. 1 i~ a schemat,ic diagram representing one example of track patterns which are produced in accordance with the presen~ invention;
~ IGS. 2A-2F are timing diagr~ms represen~ing ~he various signals that are recorded in the data and control ~racks of the record medium in accordance with the present invention;
FIGS. 3A-3C are tables which are helpful in understanding the relationship among the different formats with which the present invention can be used;
F~G. 4 is a schema~ic diagr~m repxesenting the arrangement of recording and playback transducers which may be used t with the advantages derived from the present invention, in carrying out an edit operation;
FI~. 5 is a block diagram of one embodiment of the recording 6ection in which the present invention is used, - FIG. 6 is a block diagram of one embodiment of the r~producing ~ection in which the present invention finds ready application; and FIGS. 7A-7D are timing charts which are useful in understanding one advantage of the present invention.

D AILED DESCRIPTION OF CERTAIN PREFER~ED EMBODIMENTS
Referring now to the drawings, and in particular to FIG. l, there is illustrated one example of magnetic tape track configurations with which the present invention can be used. It should be readily appreciated from ~he forthcoming description that this invention can be used to record digitized information on various different types of record media, such as magnetic tape, magnetic disc, magnetic sheet, optical disc, and the like. For the purpose of the present description, it is assumed that the digitized information is recorded on magnetic ~ape. It is further assumed that this magnetic tape moves with respect to fixed recording and reproducing transducers. Preferably, the recording transducers, or heads, are arranged in an assembly so as to record plural tracks concurrently.
These tracks are illustrated in FIG. l as being recorded on magnetic tape l of, for example, l/4 inch wi~dth. Although not shown herein, in other examples the tracks may be recorded on magnetic tape of one-half inch width, and the tracks also may be recorded Gn magnetic tape of one inch width. As illustrated, the respective tracks are parallel with each other and extend in the longitudinal direction along the magnetic tape.
In FIG. l, tape l is illustrated as having marginal tracks TAl and TA2 adjacent the opposite edges thereof.
These marginal tracks are adapted ~o have analog signals recorded therein. For example, when tape l is used to record digital audio signals, analog tracks TAl and TA2 are used to record analog audio signals. These analog audio signals ~z~

are useful in locating desired portions of the magnetic tape for use in editing operations, such as so-called splice editing or electronic editing.
Magnetic tape 1 is illustrated as having a center line on either side of which are provided tracks TC and TT.
Track TC is a control track adapted to have a control signal recorded therein. ~his control signal is illustrated in greater detail in FIG. 2B. Track TT is adapted to have a time code recorded therein.
Data tracks TD1, TD2, TD3 and TD4 are disposed, or sandwiched, between analog track T~l and control track TC.
Similarlyt data tracks TD~! TD6, TD7 and TD8 are disposed, or sandwiched, between tLme code track TT and analog track TA2.
It will be appreciated that the digitized information is recorded in each of the data tracks TD. In the illustrated example of 1/4 inch tape, the digitized information may be recorded in any one of difEerent formats. As an example, and for the purpose of illustration, three separate formats are described herein, these formats being referred to as ormat A, format B and format C, respecti~ely. As one example thereof, digiti7ed information is recorded in format A in one track per channel. That is, if eight channels of digitized information are provided, these eight channels are recorded in data tracks TDl-TD8, respectively. In format B, the digitized information is recorded in two tracks per channel. That is, since eight data tracks are provided, a total of four channels may be recorded, wherein channel 1 is recorded in tracks TDl and TD5, channel 2 is recorded in tracks TD2 and TD6, and so on. In format C, the digitized information is recorded in four tracks per chann~1.

_g_ Thus, with the eight data ~rack illustrated in FIG. 1, a total of two channels may be recorded, where-n digital signals from channel 1 are recorded in tracks TDl, TD3, TD5 and TD7, and digital signals from channel 2 are recorded in tracks TD2, TD4, TD6 and TD~. The particular manner in which the digital signals axe recorded in the respective tracks is described in greater detail hereinbelow.
In FIG. 1, the following representations are used for the indicated dimensions:
a = data track pitch;
b = data track width;
c = guard band width separating adjacent data tracks;
d = clearance between adjacent analog and data tracks from the edge of the analog track to the center of the adjacent data track e = analog track width, and f = tape width.
A numerical example of the foregoing dimensions follows:
a = 480 ~m (microns~
b = 280 to 380 ~m c = 200 to 100 ~m d = 540 ~m e = 445 ~m f = 6.30 mm~20 ~m It may be appreciated that, when ormat A is used such that one track per channel is used for recording, the magnetic tape is advanced at a speed referred to herein as its highest speed. When format B is used such that two ~l~Z~

tracks per channel are employed for recording, the tape speed may be reduced by half, and this lesser speed is referred to as the medium speed. When format C is used such that four tracks per channel are utilized for record-ing, the tape speed may be reduced by one~half again, andthis is referred to as the slowest tape speed. A numerical example for tape l, having 1/4 inch width, is as fQllOWS:

Format A Format B Format C
. _ _ lO Number of channels 8 ~ 2 Number of tracks per channel l 2 4 Tape speed (cm/sec) 76.00 38.00 19.00 It is appreciated that, when more tracks per channel are used, the tape speed may be reduced, ~hereby reducing tape consumption and enabling so-called long-playing tapes.
However, as tape consumption is reduced, thereby increasing the playiny time, the number of channels which may be recorded likewise is reduced.
In the foregoing table, the digiti~ed information recorded in the respective data tracks is derived from analog signals, these analog signals being sampled at a predetermined sampling rate and each sample being converted to digital form. As a numerical example, the sampling rate f5 ~5 which is used to produce the digitized information is on the order of 50.4 kHz. Other sampling frequencies f5 may be used. It is appreciated that, if lower sampling frequencies are employed, the speed at which the tape is driven for recording the digitized information in their respective 3Q formats likewise may be reduced. Thus, for a sampling frequency f5 on the order of about 44.1 kHz, the tape speed for tape 1 recording in format A may be on th~ order of about 66.5 cm/sec. ~or the sampling frequency f on the order of about 32.0 kHæ, the tape speed for the tape recording in format A is on the order of about 48.25 cm/sec.
Of course, the foregoing tape speeds are halved when format B
is adapted, and these tape speeds are halved again when format C is adopted.
Turning now to FIGS. 2A-2F, there are illustrated a typical example of the control signal tha~ is recorded in control track TC and a typical example of the digitized information that is recorded in a typical data track TD.
FIG. 2B is a timing diagram representing the control signal;
and FIGS. 2C-2F, in combina~ion, are timing diagrams representative of the digitized information.
The control signal having the timing representatlon shown in FIG. 2B is recorded in control track TC for all formats. This control signal is comprised of a synchronizing signal positioned at the head, or beginning portion thereof, followed by a 16-bit control ~ord formed of control data bits C0-Cl5, followed by a 28-~it sector address formed of address bits 50-S27, followed by a 16-bit error detecting code word, such as the cyclic redundancy code (CRC) word.
Although the control signal shown in FIG. 2B is comprised of predetermined segments each formed of a preselected number of bits, it will be appreciated that, if desired, other segmen~s may be used; and each of the illustrated segments may be iormed of any desired number of bits capable of representing control data, sector addresses and error detecting codes. Furthermore, if desired, the synchronizing signal may be positioned at any other predetermined location in the control signal.

The term l'sector" or "sector interval", as used herein, refers to a predetermined time interval which corresponds to a predetermined recording length, ox in~erval, on the record medium. The sector interval is defined by the control signal illustrated in FIG. 2B.
Successive control signals are recorded in successive~
abutting sector intervals. As each control signal is recorded in a sector interval, the sector address is incremented by unity (i. e. by one bit). Hence, the sector address serves to identiEy the particular sector lnterval in which the control signal is recorded. The desired sector interval may be accessed merely by addressing the corresponding sector address. It is appreciated that 2~8 successive sector intervals may be recoxded on, for example, a length of magnetic tape;
and the corresponding sector addresses will be incremented from one sector interval tc the next so as to appear as, for example, [000...000], [000...001], [000...010], [000...011~, and so on. As will be explained below, digitized information is recorded in the respective data tracks TD during each of the successive sector intervals.
The synchronizing signal which precedes the control word is illustrated with an expanded time scale in FIG. 2A. The synchronizing signal occupies a duration equal to four control signal bit cells, wherein a bit cell is equal to the inter~al occupied by a respective bit of the control word, the sectar address and the CRC code.

~2;~

The synchronizing signal is seen to exhibi~ a predetermined, ~onstant synchronizing pattern preceded by a "preamble".
The purpose of the preamble is to accommodate the last, or least significant bit of the CRC codel included in the imm diately preceding control signal, so as to ensure that the synchronizing pattern will appear as illustrated. For example, if the last bi~ of the preceding control signal is a binary "1", which exhibits a relatively higher level the preamble of the immediately-following synchronizing signal also is at a relatively higher binary "1" level for a duration equal to 0.5 T' (where T' is equal to the bit cell duration of a control signal bit). Conversely, if the last bit of the immediately preceding control signal is a binary "O", which is represented by a relatively lower level signal, the preamble of the next-following synchronizing signal also is equal to a relatively lower binary "O" level for this duration 0.5 T'. Hence, the preamble is seen to exhibit either a first or a second logical sense depending upon the state of the last bit of the immediately preceding control signal.
The synchronizing pattern which is included in the synchronizing signal and which follows the preamble exhibits a positive-going transition at a period lT' following the preamble, and then exhibits an cpposite, negative-going transition at a period 1.5T' following the first-mentioned positive-going transition. The synchronizing signal ends, and the control word commences, at a period lT' following this second, negative-going transition. This particular synchronizing pattern is advantageous in that it ~1~--~ ~22~

is distinct from any bit pattern included in the control word, sector address or CRC code of the contlol signal.
~ence, this synchronizing pattern may be readily detected during a reproducing operation so as to identify the beginning of successive sector intervals. Also, this synchronizing pattern, when detected, may be used to synchronize the detection of the control word, sector address and CRC code of the control signal, and also may be used in a servo control circuit for controlling the tape drive during a reproducing operation. When the pres~nt invention is used with a magnetic recording medium, the transitions in the recorded signal, such as the illustrated transitions which comprise the synchronizing pattern, represent magnetic vectors.
The control word is adapted to represent control data for the purpose of identifying ~he particular format that is used to record the digitized information. For example, control bits C12-C15 may represent the sampling rate that has been used to digitize the analog signal, resulting in the digitized information that is recorded.
Alternatively, since the speed at which the record medi.um is driven is related to the sampling rate, control bits C12-C15 may represent this tape speed. As an example, for the three representative sampling rates mentioned above, ~5 control bits C12-C15, ~hich are referred to her~in as ~he sampling rate identification signal may be as follows:

Sampling Rate Identification Signal Sampling Rate (kHz~

C15 C14 C13 C12 ~s ~ 0 0 0 50.4 0 0 0 1 4~.1 0 0 1 ~ 32.0 It is seen that, i desired, up to sixteen different sampling rates may be accommodated by the sampling rate identification signal (C12 C15~
Control bits Cg-Cll represent the number of tracks per channel in which each channel of digitized information is recorded. From the description set out hereinabove, it is recalled that in format A, each channel of digitizPd information is recorded in a respective data track. In format B, each channel of digitized information is recorded in two geparate data tracks. In format C, each channel of digitized information is recorded in four separate data tracks. The number of tracks per channel may be represented by control bits Cg-Cll as follows:

15 Cll C10 Cg Tracks/Channel Format 0 0 ~ 2 It is appreciated that a total of eight different fo~lat charac-teristics, including the number oE tracks per channel, may be represented by the 3-bit code Cg-Cll. For purposes of illustration, and in the interest of simplification and brevity, only three such characteristics ~i. e~ tracks per channel) are illustrated.
Control bits C0-C8 are used to represent other elements which constitute respective formats. For example, different encoding schemes may be used to encode the digitized information. Such encoding ~chemes include the %

aforementioned cross-interleave eode. ~odifications of the cro~s-interlea~e code also may be used, as desired. Further-more, an encoding scheme which is adapted to minimize dis-tortion due to the DC component of the digital signals recorded on the record medium al~o may be ~sed, ~uch as de~cribed in Application Serial No. 361,507, filed October 3, 1980, the disclosure ~hereof being incorporated herein by reference.
Other examples of interleaved error correction encodiny techniques are described in, for example, U- S- Patent .~o. 4,355,392, lssued October 19, 1982, Canadian Patent Applications 361,558, fil~d Octobex 3, 19~0, 369,129, filed January 23, 1981 and 371,637, ~iled February 24, 1981, the disclosur~s oE which beinq incorl~orated herein by reference.
In addition to being encoded in a desired encoding ~cheme, which encoding 6cheme is represented by selected oneR of data bits C~-Cg, the encoded digi~ized information also may be modulated prior to recording. One example of a type o~ modulation that may be u~ed is described in U.S. Patent No. 4,369,472, Issued January 1, 1983.
In thi~ modulator, the encoded digital ~ignals are modulated BO ~B to establi~h strict limi~tations on the minimum and maximum ~ntervals between successiva transitions t thereby avoiding distortion whe~ the digitized 6ignals are reproduced, 2S O~ course, other types of modula~ion may be used, such as the ~o-called 3PM type, or MFM type, or ~i-phase modulation, as de6ired. The particular type of modulation which is u~ed is represented by ~elected ones of control blts CQ-Cg, -~7 Thus, it is appreciated that the control data comprised of bits CO-Cl5 represent the particular format which is used to sample, encode, modulate and record the input information.
The sector address comprised of bits SO~S27 may be generated by, for example, a typical counter that is incremented in synchronism ~ith the processing and recording of each sector interval. Preferakly, the control data and the sector address data are used to produce an appropriate CRC code, or other error detecting code, from which the presence of an error in the control word and/or sector address may be detected upon reproduction.
The formation of a CRC code and the manner in which it is used are kno~l to those of ordinary skill in the art and, in the interest of brevity, further description thereof is not provided.
As will be described below, the control signal illustrat.ed in FIG. 2B is subjected to FM modulation, and the FM-modulated cont.rol signal then is recorded in control 20 tlack TC~ Thus, regardless of the particular format which is u~ed to record the digiti~ed information, the E'M-modulated control ~ignal described he.reinabvve is common to s~lch diferent formats.
FIG. 2C is a representative tim.ing diagram ~5 illustrating the manner in which digiti~ed information is reco.rded in a respective data track TD. For simplification, reference is made initially to the recording of digitized information in one track per channel~ In accordance with ~18-the aforementio-ned cross-interleave error correction encoding techniques, successive samples of an inpu~
analog signal, such as an audio signal, are converted to corresponding digital information words, and these digital informa~ion words are used to produce error-correction words, such as parity words P~ Then,, a pre-determined number of information words and parity words are time-interleaved to form sub-blocks, and a further error-correction word, such as a ~-parity word, is derived from the time-interleaved sub-blockn Odd and even information words and their respecti.ve P-parity and Q-parity words are cross-interleaved to form a data block comprising, Eor example, twelve information words, four parity words and an error-detection word, such as a CRC code wordr derived therefrom. A respective data block is preceded by a data synchronizing signal and, as illustrated in FIG. 2C, four successive data blocks ar0 recorded in a sector interval. Of course, the data blocks may be modulated prior to recording, as clescribed above.
When format A is used, wherein the digiti~ed information is recorded in one track per channel, successi~e data blocks are recorded in seriatum in a corresponding data track TD. When the digitized information is recorded in ormat B, wherein two tracks per channel are used, each of these two data tracks is provided with successive data blocks as shown in FIG~ 2C b Howeverl such recorded data blocks need not necessarily be sequential blocks.
For example, the first data block may be recorded in block position ~1 ~in a first of the two tracks, and the ~z~

second data block may be recorded in block position ~1 in the second data track. Then, the third data block may be recorded in block position #2 in ~he first track and the fourth data block may be recorded in block posi-tion ~2 in the second data track. This distribution ofdata blocks may continue such that, for example, in khe first data tr-ack, data blocks 1, 3, 5, 7 and so on are recorded; and in the second data track, data blocks 2, 4, 6, 8 and so on are recorded.
I~ format C is selected, wherein four traclcs per channel are used Eor recording, the first data block .is recorded in block position #l of a first data track, the second data block is recorded in block position #1 of a second data track, the third data block is recorded in block position #1 of a third data trackl and the fourth data bloc}c is recorded in block position #l of the fourth data track. Then, the f.ifth data block is recorded in block position #2 of the first data track, the sixth data bloclc is recorded in block position #2 of the second data track, the seventh data block is recorded in block position ~2 of the third data track and the eighth data block is recorded in block position ~2 of the fourth data track. Hence, the irst data track has recorded therein the data blocks o sequence 1, 5, 9, 13, and so on; the second data track has recorded therein the sequence of data blocks 2, 6, 10, 14, and so on; the third data track has recorded therein the sequence of data blocks 3, 7, 11, 15 and so on; and the fourth data track has recorded therein the sequence of data blocks 4, 8, 12/ 16 and so on.

-ZO--~8~

Nevertheless, regardless of the particular format, or nurnber of tracks per channel which is u~ed, each data track has succeeding data blocks recorded therein in the manner shown in F~G. 2C. Thus, during each sector interval, four succeeding data blocks are recorded, each data block being preceded by a data synchronizing signal. Advantageously, the control signal recording head is in proper alignment with the information signal recording heads such that all of the data tracks are in alignment across the width of the magnetic medium, that is, all of the data synchronizing signals are in alignment, and the information signals also are in alignment with the control signal recorded in control track TC. That is, the synchronizing signal which is xecorded at the head cf the control signal is in alignment with the data synchronizing signals of each of the first data blocks recorded in a particular sector interval. Alternatively, the contxol signal recording head may be displaced from the information signal recording heads by a distance equal to an integral multiple of a sector interval.
The data synchronizing signal which precedes each data block (shown by the cross-hatched areas in FIG. 2C~ is illustrated with an expanded time scale in FIGS. 2D and 2E.
~he data synchroni~ing signal occupies an interval corresponding ~S to sixteen clata bit cells, wherein each data bit cell is equal to the duration of the recorded data bit. It should be appreciated that the duration of a data bit cell T is much smaller than the duration of a control bit cell T'~

for example, T' = 18T. The data ~ynchronizing signal in-cludes a 6ynchronizing pattern comprised of a first tran~ition which occurs at an interval 1.5T following the beginning of the data synchronizing ~ignal t a ~econd tran~ition which occurs at an interval 405T ollowing the first transition, and a third tranBition which occurs ~t an interval 4.5T ollowing ~he second txansi~ion.
Since the data ~ynchrcnizing ~ignal of one data block follow~ immediately after the last bit of the preceding data block, the ~ynchronizing pattern may exhibit the waveform ~hown either in FIGS. ~D or 2E,depending upon the logic ~ignal level of the final bit of the preceding data block.
The data synchronizing pattern is selected ~o be unique in that this pattern will not be exhibited by the information data .included in the respective data blocks, even after modulation~ For example, if the modulation descr~ in U.S. Pat~nt No. 4,369,472 Issued Janu~y 18, 1983 is adop~, ~c~nsi~ons between data bits of the modulated d.igiti~ed inormation ~0 are prohibited from exhibiting the pattern 6hown in FIGS. 2D
~nd 2E. Conse~uently, the data ~ynchronizing ~ignal snay b~ readily detected upon reproduction and used, for example, tn re~tore timing, to detect the beginnin~ of a data block, to ~nchronize the demodulation and decoding of the d.igitized information, and the like.
The data synchronizing pattern i~ follvwedt aftQr a delay interval o 0.5T~ by a block ~ddre~s compri~ed of bits Bo-B2 which, in turn, i~ ollowed by flag bitæ FBl and FBo.

2~

The block address [s2BlBo] id~ntifies the particular block position in which the data block is recorded. Preferably, the most significant bit B2 of the block address is made equal to the least 6ignificant bit S0 of the sector address of the particular sector in which the data block is recorded.
If the block address is comprised of, for e~ample, four bits, then the two most significant bits thereof may be made equal to the two lea.st sign:ificant bits SlS0 of the sector addres~. With the block address comprised of three bits, it is appreciated that eight separate block p~sitions may be represented thereby. Since four data blocks are recorded in a sector interval, and since the most significant block address b.it B2 is made equal to the least significant sector address bit S0, it is appre-ciated that the block address [B2BlBo] .is repeated everytwo sector intervals, but that portion of the b:lock address [BlBo] i5 repeated at every sector interval.
That is, eight separate block positions are recorded dur:ing every two sector intervals. If the most significant block address bit B2 is equal to a binary "1", as determined by the lea~t significant sector address bit S0, then the data 3ynchronizing signal shown in FIG. 2D is recorded. Alter-natively, if the most significant block address bit B2 is equal to a binary "0", then the data synchronizing signal illustrated in FIG. 2E is recorded.
Flag bits FBl and FBo are used, in the preferred embodiment of the present invention, as an emphasis :~8~

identification signal. Preferably, when the present invention is used to record digital audio signals, the original analog audi.o ~ignals are selectively subjected to emphasis prior to being digitized. If such analog signals are emphasized, that is, if a conventional emphasis circuit is actuated or "turned on", then the emphasis identification signal represents that the analog signal had been emphasized.
For example, [FBlFBo] = [01]. Alternatively, if the input analog signals had not been emphasi~ed, then the emphasis identificat.ion signal may be represented as lF131F:130] = [00], Typically, emphasis will occur over a sufficient duration such that all of the digitized signals from a particular channel which are recorded in two sector intervals will be emphasized. It is, therefore, not necessary to record t~e emphasis identification signal in each data block.
Preferably, therefore, the emphasis identification signal i~ recorded only when the block address [B2BlBo] is equal to [000].
Furthermore, if the digitized information is recorded in two ~ tracks per channel, the emphasis identification signal may b~ r~corded only in one of such two tracks/ and as b~Eore, th~ emphasis .identification signal is recorded only when the block address in that particular track is equal to [000]
Likewise, when the digiti~ed information i9 recorded in 2S four tracks per channel, the emphasis identification signal may be recorded in only a predetermined one of those tracks and, again, only when the block address in that ~rack i5 equal to ~000]. Consequently, flag bits FB1 and FBo may be used to represent other information, or format data, as desired, when the block address is other than [000].

Although the emphasis identification signal has been described herein as being recorded in the first data block of, for example, even-numbered sector intervals (S0 - ""): the emphasis identification signal may, if desired, be recorded in the first data block in odd-numbered sector intervals (S0 = l'l").
As illustrated in FIGS. 2D and 2E, the data synchronizing signal interval is equal to a 16~bit interval which, in turn, corresponds to an information (or parity) word duration.
The information portion of each data block is il.lustrated with an expanded time scale in E'IG. 2F. In-formation words Wl-W12 each is formed as a 16-bit word, and each is derived from a respective sample of the input analog signal. In addition to the information words Wl-W12, each data b~ock also includes odd and even parity words P0 and PE, respectively, and odd and even Q-paxity words Q0 and QE, respectively. The odd and even information and parity words are cross-interleaved in accordance wi.th the techniques described in the above-.referenced, i.ncorporated patent applications. In addition, an error detecting word, ~uch ~S a 16-bit CRC code word, is produced in response to kh~ information and parity words, and also in response to the block acldress bits Bo--B2 and the flag bits FBo and FB~.
It will be appreciated that i.nformation words Wl-W12 all are derived from the same channel. Odd-numbered and even-numbered information words are separated, and the respective parity words Po~ PE and QO~ QE are derived from such separated information words~ For example, odd parity word PO is produced in response to the 5iX odd-numbered information words W], W3 ... Wll; and even parity word PE
is produced in response to the 5iX even-numbered informa-tion words W2, W6 ... W12. The odd-numbered information and parity words are time-interleaved, and the odd parity word QO is produced therefrom. Likewise, the even-numbered information and parity words are time-interleaved, and the even parity word QE is produced therefromO Then, all of these time-interleaved odd and even words are cross-interleaved to form the illustrated data block. Preferably, the parity words are positioned in the central section of the data block, and successive odd-numbered (and even~numbered) information words are spaced from each other by a maximum distance. Thus, successive odd-numbered information words Wl and W3 are seen to be separated by the maximum distance which can be accommodated by the data block. Likewise, 6uccessive even-numbered information words W2 and W~ are separated by this maximum distance. This cross-interleaved error correction encodiny technique facilitates the cvrrec-tion of what otherwi.se would be considered to be "uncorrectable"
exrors wherein successive information words are oblite:rated.
Since there is a low probability that, for example, infor-matiQIl words Wl and W3 both will be obliterated, when vnly one of these words is erroneous, it may be derived by .intelpolation techniques from the non-erroneous information words.
From the aforementioned patent applications, it will be appreciated that information words Wl and W2, for example, do not correspond to adjacent samples of the input analog signal. Such adjacent samples may be -2~-represented by information words that are recorded in widely separated data blocks. This is an advantageous feature of the aforem~ntioned cross-interleave error correction encoding technique.
FIGS. 3A-3C illustrate the relationship among the recording foxmats A, B and C, respectively/ wherein each channel of digitized information is recorded in one data track (forma~ A), in two data tracks (format B) or in four data tracks (format C~. ~rhus, in format A, as 8hown in FIG. 3A, successive data blocks are recorded in a single data track. In format B, as shown in FIG. 3B, successive data blocks are distributed alternately between tracks A and B. In format C, successive data blocks of a single channel are distributed, sequentially, in data tracks A, B, C and D. This distribution of data blocks in respective data tracks will be described in greater detail hereinbelow.
In FIGS. 3A-3C, the expression "data sequence"
re~ers to the successive data blocks included in a particular channel, and the expression "block address" refers to the block ~ in which that particular data block is recorded in n xespective data track. Furthermore, the expressions "n"
and "m", as used in FIGS. 3A-3C, are integer3. Accordingly, it is seeo that, when format A is adopted, the first data block ~n) is recorded in block #0 of, for example, the first sector interval (4m + 0). The second data block ~n + 1) is recorded in block #1 of this sector interval, and BO on. In the second sector interval ~4m t 1), the fifth data block (n + 4) is recorded in block #4, the sixth data block (n + 6) is recorded in block ~5, and so on.
At the next-following sector interval (4m + 2), the block addresses are seen to repeatO

Z~3l2 When format B is adopted, the first data block (n) is recorded in block ~0 of track A in the first sector interval (4m ~ 0), and the second data block (n ~ 1) is recorded in block #0 of track B in this sector interval.
The third data block (n + 2) is recorded in block $1 OE
track A in this sector interval, and the fourth data block (n ~ 3) is recorded in block ~1 of track B in this sector interval. This distribution of data blocks continues such that, in block ~0, 1, 2, 3, 4, 5, 6 and 7 of ~rack A, data blocks n, n -~ 2, n ~ 4, n ~ 6, n ~ 8, n ~ 10, n +12, and n ~ 14 are recorded; and in block #0, 1, 2, 3, 4, 5, 6 and 7 in track B data blocks n + 1, n ~ 3, n ~ 5, n + 7, n + 9, n + 11, n + 13 and n + 15 are recorded.
It is seen that these block addresses repeat at the commence-ment of sector interval 4m + 2.
When format C is adopted, as shown in FIG. 3C,the successive data block~ are distributed in tracks A, B, C and D. Thus, the first data block (n) is recorded in block $0 of track A, the second data block (n ~ 1) is recorded .in block $0 o track B, the third data block (n ~ 2) i~ xecorded in block #0 o track C and the fourth data bloc]c (n ~ 3) is recorded in block #0 of track D. This sequence o~ data block distributions continues, 60 as to record the data blocks in respective block numbers o tracks A-D, respectively, as illustrated. Upon the occurrence of sector interval 4m ~ 2, the block addresses in each of tracks A-D repeat.

The foregoing may be summariæed, when the record medium is, for example, 1/4 inch width tape, as follows:

Data Track Format A Format B Format C
__ ~ __ TDl C~l C~ A CHl-A

TD3 CH3 CH3-A CHl~C
TD4 CH4 CH4-A CH~-C
TD5 CH5 CHl-B CHl-B

TD7 CH7 CH3-B CHl-D

In the foregoing, it is seen that, when format B is adopted, the first data block (A) for channel 1 (CHl) is recorded in data track TD1, and the second data block (B) of channel 1 (CHl) is recorded in data track TD5. A similar distribution occurs for channels 2-4.
When format C is adopted, the first data block (A) ~0 of channel 1 (CHl) is recorded in data track TDl, the secolld clata block (B) of channel 1 (CHl) is recorded in data track ~'D5, the third data block (C) of channel. 1 (CHl) ls xecord~d in data track TD3, and the fourth data bloc]c (D) o channel 1 (CHl) ~s recorded in data track TD7. A similar distribution of successive data blocks A, s, C and D or channel 2 is recorded in data tracks ~D2, TD6, TD4 and TD8, respectively.
The foregoing track assignments advantageously simplify the manner in which data is distributed or re-covered for the different formats which may be used.

2~2 FIG. 4 schema~ically illustrates one example of the recording transducers, or heads, which a-e used for recording digitized information in the respective data tracks, as we].l as for recordlng the control signal in control track TC. The arrangement shown in FIG. 4 is particularly adapted to enable the information recorded in one track to be re-recorded in another track; and also to enable electronic editing, wherein info.rmation from a separate source, such as another record medium, i~ inserted into one or more desired data tracks at punch-in points. For the embodiment shown :in FIG. 4, maynet.ic tape 1 is ass~lmed to be driven in the direction indicated by the arrow.
The heads of FIG. 4 are comprised of a set of recording heads HR, a set of reproducing, or playbaclc heads HP
and another set of recording heads HR'. Each set of heads is comprised of aligned heads which are used for recording ox rep.roducing information in respective data tracks TD, and also the control head for recording or reproducing the control sig.nal in control track TC. Thus, recordiny heads HR actually are cornprised of separate recording h~d~ HRl-HR~ together with control signal recordiny head HRC, all aligned across the width of tape 1. Lilcewise, additional recoxding heads HR' actually are comprised of recordirly heads HR'l-HR'8 and control signal .recording ~RIc.
Recording heads HR are used to record original information in the respective data and control tracks of tape 1. Fox example, these heads may be used to form an 2~

original recoxding. The information recorded in these track6 are reproduced by associated ones of reproducing heads ~B. ~hen information recorded in one or more track6 i5 to be edited, ~hat i6, this information is to be modified or replaced by ~dditional information, recording heads HR' Are oper~ted, ~electively, to record ~uch additi~nal information in the appropriate tracks. For example, in format A, the digiti~ed inform~tion xecording :in track TDl may be edited by locating the d~sired punch-in point and then, when that punch-in point reaches recording head ~IR'l, he new information i5 recorded in data track TDl. When the desired punch-out point i~ reached, xecording head HR'l is disabled. I,ikewise, when information recoxded in one channel, or one track, is to be re-recorded in another channel, or track, the inormation from the fir6t channel, or track, is reproduced by the appropriate ones of reproducillg heads ~, and that reproduced inormation then is supplied to the desired ones of recording heads HR' for re-recording in the appropriate ~0 tr~cks. The combination of heads ~IP and HR' may be u~ed ~ox ~o-called "~ync" recording wherein one channel is recorded while another channel i~ reproduced. It will be appreciated that, even when the foregoing edit operations ox t'~ync" recording is carried out, the control track iA
no~ modi~i~ied.
Typical examples of electronic editing which may b~ used with the arrangem~nt of the transducer~ shown in FIG. 4 are described in ~. ~. Patent No. 4,327,382 Issued April 27, 1982, and also in ApplicatiQn Serial No. 361,558, ~31-2~L2 filed October 19, 1980.
Turning now to FIG~ 5, ~here is illustrated a block diagram of one embodiment of apparatus which may be used to record digitized information in a selected one of various different formats. This digitized information may represent digital audio signals, ~uch as PCM audio ~ignals, which have been oonverted into digital form in accordance with a selected ~ampling rate ~, and which have been selectively emphasized in accordance with a conventional emphasis circuit.
The illustrated record.ing apparatus i5 adap~ed to r~cei~e up to eight channel~ of diyi~ized information, and to record the received channels of informa~ion in respective data tracks. As mentioned above, the number of tracks in which each channel of information is recorded is dependent upon the ~elected format. Accordingly, the illustrated apparatus is provided with eight input terminals 2a...2h~ each adapted to receive a respective channel of digitixed information CHlu..C~8, respectively.
Input terminals 2a-2h are coupled to encoders 3a-3h, re~pec~ively.
Each encoder may be of tne cross-interleaved error correction typ~ described hereinabove or, alternatively, the encoders may be adapted to enGode the digiti~ed infor-mation in other error correction encoding ~cheme~. Each encoder may be operable in accordance with different format~ ~uch that a particular encoding ~cheme i~ adopted in accordance with a format identifying signal ~upplied thereto.

~32-~8~

For this purpose, an additional input terminal 4a is provided to receive a format control signal which may be generated by, for example, an operator of the illustrated apparatus.
In order to sirnplify the present description, it is assumed that only one type of encoding scheme is used, such as the aforementioned cross-interlea~ed error correction code. Thus, regardless of the format which is selected, this same encoding scheme will be employed to encode each channel of digitized information. ~owever, it is contemplatecl t~at different encoding schemes may be used to accommodate different formats. The particular encoding scheme which is selected, that is, ~he par~icular mode of operation of the illustrated encoders, is dependent upon the format control signal sùpplied to such encoders from input terminal 4a.
The encoded digitized information produced by encoders 3a-3h are supplied to respective inputs of a demultiplexor 6. This demultiplexor is adapted to distribute the digitized information supplied to the respective inputs thereof to preselected outputs, depending upon the par~icular format which has been selected. In this regard, demultiplexor 6 is coupled to a controller 7 which, in turn, is coupled to input terminal 4a to xeceive the Eormat control sign~l~
In one embodiment the demultiplexor includes a ~5 set of switching circuits, the operation of which is controlled by controller 7. For example, if the format control signal supplied to input terminal 4a identifies format A, controller 7 controls the switching circuits of demultiplexor 6 such that the digitized information supplied to each input of the demultiplexor from encoders 3a 3h, respectively, is coupled to a corresponding respective output. That is, each channel of digitized information is distributed to only a single output of demultiplexor 6.
If, however, the format control signal supplied to input terminal 4a identifies ~ormat B, controller 7 controls demultiplexor 6 to distr.ibute each channel of digitized inform~tion supplied to a respective input to two outputs.
In this regard, only four channels (CHl-CH4) of digitized information are supplied to the illustrated recording apparatus.
Each channel is distributed to two respective outputs of the demultiplexor in accordance with the foregoing table.
Likewise, if the format control signal supplied to input terminal 4a identifies format C, controller 7 controls the switching circuits of demultiplexor 6 such that each channel of digit.ized .input information supplied to the demultiplexor is distributed to four respective outputs. When format C is adopted, it is appreciated that only two channels (CHl and CH2) of digitized information are supplied to the ;llustrated recording apparatus. Demultiplexor 6 is controlled so as to distribute these channels of digitized infoxmatiorl in th~ m~nner summarlzed by the foregoing table.
In the foregoing description, it should be recognize~ that the digitized informatiorl supplied to each input of demultiplexor 6 is encoded in, preferably, the cxoss-interleaved error correction code by encoders 3a-3h, respec-tively. Thus, a particular input of the demultiplexor is -~3~-ZZ~L~

supplied with consecutive data blocks of the type ~hown in ~IG. 2F, each data block having been formed in the manner described in the aforementioned, patent ~pplications.
The outputs of dPmultiplexor S, which also may be referred to a~ a distributor circuit, are coupled ~o modulators Ba-8h, respectively. ~ach modulator may be of the tyFe described in aforementioned United States Patent No. 4l369,472. Although not shown herein, each modulator alternatively may be adapted to operate in dif~erent modes o~ operation ~o as to carry ou~ different ~ypes of modulation.
The particular type of modulation which i5 adopted i5 dependent on and controlled by the format control signal ~upplied to input terminal ~a. Thus, depending upon the particular format which is adopted by the operator, a corresp~nding type of modulation is effected.
The outputs of modulators 8a-8h are coupled to dat~ rec~rding heads ~Rl-HRB via recording amplifiers 9a-9h to be recorded in clata tracks TDl-~D8, respectively.
~hus, each received channel o~ digitized information is recorded in thc ~elected format onl for example, magnetic tape. ~hat i~, a selected encoding ~cheme, type of modulation, tape 6peed and number o~ tracks per channel are adopted in accordance with the particular ormat which is used FIG. 5 also illustrates a control channel whereby ~he control ~ignal shown in FIG. 2B is produced, modulated and recorded in a separate control track TC. The contxol channel is coupled ~o input terminal 4a and also to o3~-additional input terminals 4b and 4c. Input terminal 4b is adapted to receive a sampling identification signal which identifies, or represents, the particular sampling xate fs which has been used to digitize the original input analog information. Input terminal 4c is adapted to receive an appropriate clock siqnal for synchronizing the operation of the control channel. These input termianls 4a, 4b and 4c are connected to a control signal encoder 5 which, for example, includes a control word generator responsive to the format control signal and the sampling identification signal to produce the aforementioned control word comprised of control bits C0-Cl5. The control signal encoder also includes a synchronizing ~ignal generator for generating the preamble and synchronizin~
pattern shown in FIG. 2A in response to the clock signal supplied to input terminal 4c. In addition, the control signal encoder includes a sector address generator which, preferably includes a multi-bit binary counter, such as a 30-bit counter. Also included in control signal encoder 5 is a CRC word generator which may be o$ a conventional type and which is supplied with the generator control woxd and ~ector address to produce an appropriate CRC word.
The control signal produced by control encoder 5 and which m~y be of the type shown in FIG. 2B, is coupled tv ~5 control recordin~ head HRC ~ia an FM modulator 10 and a recording amplifier 11. It is preferred to record the control signal as a frequency~modulated signal so as to facilitate the reproduction and detection thereof for all formats. That is, even though the tape speed may differ from one format to another, the frequency-modulated control signal may, nevertheless, be accurately detected.

Although not shown in FIG~ 5, each of the encoders 3a-3h includes a data synchronizing signal generator for generating the data ~ynchronizing signal illustrated in FIGS. 2D and 2E.
That is, the particular synchroniziny pattern shown in FIGS. ZD and 2E is generated by each encoder. Fuxthermore, each encoder is adapted to supply the block address lB2BlBo]
for identifying the particular blocks which are recorded in each sector interval in each data track. This block address i8 derived from, for example, the three least significant bits included in the 30-bit counter of encoder 5. Thus, this 30~bit counter i5 seen to generate both the sector address and the block address. ~ence, this counter may be incremented in synchronism with the generation, or formation, of each data block produced by encoders 3a-3h.
It is appreciated that, after Eour data blocks have been generated, the two least significant bits of the 30-bit counter repeat their cycle. Likewise, after eight data blocks have been generated, the three least significant bits of the 30-bit counter are repeated. Hence, the aforcmentioned block and sector addresses are generated b~ this 30-bit counter.
From the foregoing, it is appreciated that the same block address is recorded for each data block that is recorded in the same relative position in a sector interval in each of the plural data tracks. That is, if format A is adopted, then the same sequenti~l~block addresses [000]
[001~, 10101, ... [lll]are supplied to e ch encoder 3a-3h to be added to each data block generated thereby. Alternatively, if format B is adopted, then, for the first two data blocks generated by, for example, encoders 3a-3d, t~e block address [000] is added thereto~ Hence, although eight data blocks are xecorded, representing digitized information in four channels, all eight of these data blocks exhibit the same block address [0003. Then, for the next two data blocks produced by each of encoders 3a-3d, the block address supplied to such encoders is equal to ~001].
This block address generation continues, wherein the same block address is added to every two data blocks generated by each encoder~
If format C is adopted, it is appreciated that the same block address, as generated by the 30~bit counter included in encoder 5, is supplied to, for example, encoders 3a and 3b, for four successive data blocks generated thereby.
It is appreciated that these four data blocks generated by, for example, encoder 3a, all are encoded in substantial allgnment in the same sector interval in, for e~ample, data tracks TDl, TD5, TD3 and TD7, respectively Each of these data blocks will be provided with the hlock address [000].
I,ikewise, for the first four data blocks generated by encoder 3d, the same data block address [000] will be added to those four data blocks which are recorded in data tracks TD~, TD6, TD4 and TD8, respectively. Of course, ~hese four ~ata blocks will exhibit substantial alignment in the same sector interval.
Thus, those data blocks which are located in the same relative position in a sector inte~val in all o~
the data tracks contain the same block address from ~3~-one data track to another~ The Eirst data blo~k recorded in all of the tracks, regardless of the format, includes the block address [000], the second data block in each of these tracks, regardless of the particular channel from which that data block is derived~ contains the block address [001], and so on.
It is appreciated that the 30-bit counter included in encoder 5 which is used to generate the sector and block addresses may be incremented by a clock signal supplied thereto, which signal has a period equal to a block period and which is in synchronism with the digital signals that are applied to input terminals 2a-2h.
Although not shown herein, each of encoders 3a-3h also may include an emphasis identiEication generator for generating the emphasis identification signal FBlFBo, described above.
It will be appreciated that the timing of the encoders is a function of the particular fo~lat which has been adopted. In this regard, a suitable timing control circuit, including an adjustable clock generator, may be prov~ded in each encoder, the operation of each timing control circuit being controlled, or changed over, in xesponse to the format control signal supplied to input t~rminal 4A. Thus, proper timing of the encoded digitized ~5 information is achieved so as to be consistent with the selected format.

-3g 2~2 Referring now to FIG. 6, there is illustrated a block diagram of reproducing apparatus for reproducing the digitized information from respecti~e tracks of the record medium, which apparatus is compatible with any one of the particular formats which may be used to record that information. This embodiment of the data reproducing apparatus is comprised of reproducing heads HPl-HP8 adapted to reproduce the digitized information which had been recorded in data tracks TDl-TD8, respectively. ~eads HP1~HP8 are coupled to demodulators 16a-161l via playback amplifiers 12a-12h and clock signal extracting circuits 14a-14h, respectively. Each clock signal extracting circuit includes a phase-locked loop for generatins a clock signal of desired repetition rate, which phase-locked loop is synchroni~ed with, for example, the bit timing rate, or phase, of the repro-duced digital signals. The synchronizing pattern recorded i~ the respective data tracks At the head of each data block may be used to synchronize the phase-locked loop. Hence, the bit timiny, or clock si~gnals, are extracted from the data which is reproduced from each track.
Eac}l demodulator is adapted to be compatible with th~ particular type ~f modulation which had been used to record th~ diyiti2ed information. Consequently, each demodulator may include selectable demodulator circuitry responsive to a format identification signal (such as represented by control bits C0-Cl5 of the recorded control signal) to select the appropriate demodulating circuitry.

~4-0-~2~
Demodulators 16a-16h are coupled to respective inputs of a multiplexor 21 via time base error correctors 22a-22h, respectively. Multiplexor 21 is controlled by a suitable controller 20, this controller being responsi~e to a decoded format identification signal for establishing the appropriate switching sequences for ~he multiplexor.
The outputs o~ multiplexor 21 are coup]ed to decoders 24a-24h, respectively, which decoders may be of the type described in the aEorementioned incorporated patent applications adapted to decode, for example, the preferred cross-interleaved error correction code which had been used to record the digitized information. The outputs of decoders 24a-24h are coupled to output terminals 25a-25h, respectively, so as to recover the original channels of digitized informa-tion CHl-CH8, respectively.
The reproducing apparatus shown in FIG. 6 also includes a control channel adapted to recover the control signal (FIG. 2B) which had been recorded in control track TC.
In this regard, the control channel includes a control ~0 reproducing head ~IPC coupled to an FM demodulator 17 via ~ playback amplifier 13 and a clock signal extracting Cll`CUit 15. This clock signal extracting circuit may be similar to an~ one of aforedescribed clock signal extracting circuits 14a-14h. 'rhe E'M demodulator is adapted to demodulate ~5 the control signal which had been frequency modulated prior to recording. This demodulated control ~ignal then is supplied to an error-detecting circuit 18, such as a CRC check circuit, --4:L,--which operates in a known manner in response to the CRC
code word included.in the control signal for the purpose of detecting whether an error is present in the control signal. That is, CRC check circuit 18 detects whether the control word C0-~15 or the sector address S0-527 contains an error. If no error is detected, ~he control ~ignal is supplied to a decoder 19 which operates to recover the control word (C0-Cl5~, the sector address and the synchronizing pattern included in the control signal. However, if an error is detected in the reproduced control signal, an immediately preceding control word, which had been stored to account for the possibility that the next-following control signal ~ay be erroneous, is used.
In this regard, a delay circuit having a time delay equal to one sector interval may be provided in, for example, decoder 19.
The recovered control word (C0-Cl5) i5 supplied to controller 20 to establish the part:icular switching ~rrangement for multiplexor 21, by which the digitized information which is reproduced from data tracks TDl-TD8 is r~-distributed, o.r re-ormed, back to the proper channels.
This control word also is supplied to decoders 24a-24h to selact the appropriate decoding scheme which i5 compatible with the particular encoding scheme which had been used for recording the digitized information. Also, depending upon the number of tracks per channel which had been used for recording, the timing control of the decoders may be adjusted to be compatible the7ewith, the number of tracks per channel being representedl of course, at least 2~

by control bits Cg-Cll. Also, ~he sampling identification data, comprised of bits C12-C15, may be used by digital-to-analog circuitry (not shown) so as to recover the original analog signal in each channel.
Preferably, the reproducing apparatus illustrated in FIG. 6 recovers the original digitized information, which information then is supplied to suitable converting circuitry Eor converting the digital signals back to their original analog ~orm. For example, if the illustrated appara~us is used as a so-called PCM audio recorder, the digitized information produced at the outputs of decoders 24a-24h is in the form of PCM signals, and each PCM signal is converted .into a corresponding analog level so as to re- ~rm the original analog audio signal.
Decoder 19 also recovers the control synchronizing signal (FIG. 2A) and the sector address S0-S27 included in each reproduced control signal. This control synchronizing signal, which exhibits a repetition rate determined by the sector interval, is supplied to a servo circuit for the tape-drive capstan tv effect control o~er that capstan such that the record tape is driven uniformly for the repro-duclng operation. The sector address is used to identify a particular sector interval in which a desired data block is recorded, thereby enabling precise punch-in and punch-out points to be accessed for an edit operation. The sector address also may be used to locate desired data recorded in any one or more of data tracks TDl-TD8.
Each of time base correctors 22a-22h is adapted to corr~ct time base errors which may be introduced into the -~3-digitized information in one-or more data tracks during reproduction. Such time base errors may be due to tape j.itter, expansion (or contraction~ of the tape after data has been recorded thereon, or a disturbance in the normal synchronous relationship between the data and control tracks due to, for example, editing of only one (or less than all) channel. Each time base corrector preferably includes an adAressable memory device, such as a random access memory (RAM) whose capacity is at least equal to a sector interval (i. e.
four data blocks) and~ deslrably, has a memory capacity adequate to account for maximum time base variations that may be expected. Typically, a memory capacity capable of storing eight data blocks is sufficient.
Each data block is written into the RAM of a respective time base corrector, word-by-word, in response to the extracted clock signal derived from the reproduced signal. Hence, as in conventional time base correctors, th~ .reproduced data is written into the RAM in synchronism with the ~ime base variations that may be present in the xeproduced signals. The time base correctors are coupled in common to a read clock terminal 23 adapted to be supplied with a read clock signal of fixed, reference frequency.
~ccordingly, each data block is read out o the RAM at a constant reference rate, thereby eliminating therefrom the time base variations that may have been present during reproduction.
The paxticular location in the ~M of the time base corrector in which a demodulated data block is written is a function of the block address [B2Bl~o] included in that -~4-data block. However, in the event of what may be viewed as severe time base errors caused by, for example, editing, the data blocks recorded in the edited txack may be skewed relative to the remaining tracks, and par~icularly with respect to control track TC. Nevertheless, this skew is eliminated by tlme base correctors 22a~22h. In particular, the coincidence between the most significant bit B2 of the block address and the least significant bit S0 of the sector address permits each skewed data block to be written lnto the proper location of the R~M, provided this skew is less than a full sector interval. This is better explained by referring to FIGS. 7A-7D.
FIG. 7A is a waveform diagram of the least signifi cant bits S0 of the sector address included in each periodic control signal. It is seen that this least significant bit changes over from one logical sense, or state, to the other at the sectox period. FIG. 7B illustrates the waveform of the most significant bit B2 in each bloc]c address in the absence of any skew between the data track in which this block address is recorded and the control track. Xt is ~en that the block addresses corresponding to sector l~n ar~, inde2d, present when sector address #n is reproduced from the data track. That is,least significant bit S0 and most significant bit B2 are in phase with each other.
~S Let it be assumed that the data recorded in the data track under discussion is subjected to a time base error so as to impart skew thereto relative to the control track. FIG. 7C represents this skew in the positive direction wherein the data track leads the control track. That is, the most significant block address bit B2 leads the least ~5 significant sector address bit S0 such that the d~ta blocks recorded in sector #n are reproduced almost (but less than) a full sector interval before sec~or $n is reproduced from the control track. Alternatively, FIG. 7D represents this 6kew to be in the negative direction wherein the data track lays the control track. That is, the most s.ignificant block address bit B2 lags the least significant sector address bit S0 such that the data blocks recorded in sector ~n are reproduced almost a ull sector interval after sector #n is reproduced from the contxol track. Nevertheless, in both FIGS. 7C and 7D, the most significant block address bit B2 undergoes a transition, shown as the negative transition associated with sector #n, that is less than a full sector interval from the corresponding negative transition of the lS least significant sector address b.it S0. Since the state of the most signiEicant block address bit ~B'2 or B"2) thus will coinci.de, at least briefly, with the most signiiicant sector address bit ~D~ even during this skewed relationship between the data and control tracks, the block address associated with sector #n, that i6, the block addresses th~t had been recorded in sector #n, can be readily discrimi-naked. Accordingly, the correct data blocks, as identi.fied by these block addresses, will be written into the appropriate location of the R~M. Consequently, wllen these data blocks are read out of the RAM at the Eixed read-out clock rate the aforementioned skew will be cancelled.
As described above, the data blocks read out of time base correctors 22a-22h are supplied to multiplexor 21 which operates to recover each channel of digitized information from the respective data tracks in which thcse channels were record~d. For example, if the digitized information had been recorded in format A, then multiplexor 21 supplies the successive data blocks which are applied thereto from time base correctors 22a-22h (as derived from data tracks TDl-TDB) to decoders 24a-24h, respectively. Alternatively, if the digitized information had been recorded in format B, then multiplexor 21 supplies the successive data blocks which are applied thereto from time base correctors 22a and 22e to decoder 24a, the successive data blocks which are appliecl thereto from time base correctors 22b and 22f to decoder 24b, and so on. Likewise, if the digiti~ed information had been recordedin format C, then multiplexor 21 supplies the successive data blocks which are applied thereto from 15 time base correctors 22a~ 22e, 22c and 22g to decoder 24a, and the successive data blocks which are applied thereto from time base correctors 22b, 22f, 22d and22h to decoder 24b.
The multiplexor may be of complentary construction to that of demultiplexor 6 (FIG. 5).
The decoders include CRC check circuits to de~ect if an error is present in each data bloclc applied thereto tby collventional CRC-check techniques~, de-interleaving circuits to de-interleave the digital words which constitute the respective data blocks, error-correction circuits to correct errors~ that may be present in the de-interleaved words (by using the Q- and P-parit~ words in known manner~ nd interpolating circuits to compensate, or conceal, those errors which might not be correctable (by using interpolating tech-niques of the type described in those applications which are incorporated herein by reference~. The resultant data words _~z _ 2~

produced at output termihals 25a-25h may be PCM audio signals which are converted into analog form by digital-to-analog converters (not shown) coupled to such output terminals.
While the prPsent invention has been particularly ~hown and described with reference to preferred embodiments herein, various changes and modifications in form and details may be readily apparent to those of ordinary skill in the art without departing from the spirit and scope of the invention. For example, a sepaxate synchronizing pattern need not be included as par~ of the control signal recorded in control track TC. Rather, a portion of the sector address, such as the beginning portion thereof, may perform the same function, and thus may be used as, the control synchronizing signal. As another example, the two least significant bits of the sector address may coincide with the two most signiicant bits of the data block address.
As mentioned above, s~lch coincidence permits the proper data block to be identi-Eied, even in the presence of severe skew between the data and control tracks, thereby enabling correct O data blocks to be written into corresponding locations o the time base correctors. It is intended that the appended claims be interpreted as including the foregoing as well clS other such changes and modifications.

-4~-

Claims (24)

WHAT IS CLAIMED IS:

1. A method of recording at least one channel of digitized information in at least one data track on a record medium, comprising the steps of:
generating data blocks in response to said digi-tized information, each data block containing a predetermined number of data words representing said digitized information;
generating a block address for identifying each said data block, and adding said block addres s to the data block identified thereby;
recording successive data blocks, including the block addresses added thereto, in said at least one data track;
generating a periodic control signal during successive sector intervals, said periodic control signal including at least a synchronizing signal and a sector address; and recording said control signal in a control track to define successive sector intervals on said record medium;
whereby a multiple of data blocks is recorded in said at least one data track during each sector interval.

2. The method of Claim 1 wherein said block address is comprised of plural bits and said sector address is comprised of a multiple of bits; the least significant bit of said sector address being coincident with the most significant bit of said block address.

3. The method of Claim 2 wherein said sector address is formed of a substantially greater number of bits than said block address.

4. The method of Claim 1 wherein said step of generating a periodic control signal includes generating said sector address by incrementing the previous sector address by unity substantially at the beginning of each sector interval and wherein said step of generating a block address comprises incrementing the previous block address by unity at each data block, and repeating said block addresses in successive sector intervals.

5. The method of Claim 1 wherein said at least one channel of digitized information is recorded in plural data tracks by distributing said data blocks to said plural data tracks, each data track containing said multiple of data blocks during each said sector interval; and wherein said step of generating a block address comprises generating the same block address for each data block that is recorded in the same relative position in a sector interval in each of said plural data tracks.

6. The method of Claim 1 wherein said step of generating a periodic control signal includes generating a predetermined control synchronizing pattern, and locating said control synchronizing pattern at a predetermined position in said periodic control signal.

7. The method of Claim 6 wherein said predeter-mined position in said periodic control signal is the beginning portion thereof.

8. The method of Claim 1 wherein said step of recording a block address comprises recording said block address in advance of the data block identified thereby.

9. The method of Claim 8 wherein said step of generating data blocks includes generating a predetermined data synchronizing signal, and locating said data synchronizing signal at a predetermined position in each said data block.

10. The method of Claim 9 wherein said predeter-mined position is in advance of said block address.

11. A method of recording n channels of digitized information in m data tracks on a record medium wherein each channel is recorded in m data tracks (m> n, and m and n are integers), said method comprising the steps of:
encoding the digitized information in each channel to form successive data blocks, each data block being comprised of plural data words representing said digitized information;
distributing successive ? data blocks for recording in respective ones of said ? data tracks;
generating a respective block address for each of the data blocks recorded in a respective track, said block address being incremented for each data block to be recorded in a data track, and said block address being repeated after a predetermined number of sector intervals are recorded, a multiple of data blocks being recorded in a data track in a sector interval;
recording said multiple of data blocks, including the block addresses generated therefor, in each sector interval in each of said m data tracks;
generating a periodic control signal during suc-cessive sector intervals, said periodic control signal including a sector address that is incremented for each control signal to be recorded so as to provide substantially non-repeating sector addresses, at least the least significant bit of said sector address being of the same logical sense as at least the most significant of the block addresses recorded in the same sector interval as said control signal;
and recording said periodic control signal in respec-tive sector intervals in a control track that is separate from said data tracks.

12. The method of Claim 11 wherein each channel of digitized information represents a channel of analog audio signals.

13. The method of Claim 12 wherein the plural data words included in a data block comprise PCM words.

14. The method of Claim 11 wherein said n channels of digitized information are recorded in a selected format;
and wherein said step of generating a periodic control signal includes generating control data representing the selected format, said control data being included with said sector address in said control signal.

15. The method of Claim 14, wherein said step of generating a periodic control signal further includes generating an error detecting code as a function of said control data and said sector address, said error detecting code being included in said control signal for detecting, upon the reproduction of said control signal, an error therein.

16. The method of Claim 14 wherein said step of generating a periodic control signal further includes generating a predetermined control synchronizing pattern, and inserting said control synchronizing pattern at the beginning portion of said control signal, whereby said control synchronizing pattern has a repetition rate that is the inverse of said sector interval.

17. Apparatus for recording digitized information of at least one channel in at least one data track on a relatively movable record medium, comprising:
encoding means receiving said at least one channel and generating therefrom successive data blocks adapted to be recorded, each data block including a plurality of data words representing said digitized information; said encoding means also generating block addresses to identify respective ones of said data blocks to be recorded;
recording transducer means for recording the data blocks generated from said at least one channel, together with said generated block addresses, in said at least one data track, a predetermined number of successive data blocks being recorded in said at least one data track in a sector interval;
control signal generating means for generating a control signal for recording in a respective sector interval, said control signal including at least a sector address for identifying said sector interval; and control recording transducer means for recording said control signal in a sector interval in a control track parallel to said at least one data track.

18. The apparatus of Claim 17 wherein said sector address is comprised of a multiple of bits and said block address is comprised of a plurality of bits of lesser number than said sector address; and wherein at least the least significant bit of said sector address is equal, in logical sense, to at least the most significant bit of said block address.

19. The apparatus of Claim 18 further comprising multi-bit counting means incremented when a data block adapted to be recorded is generated, a predetermined number of the bits of greater significance of said counting means comprising said sector address, and a smaller predeter-mined number of the bits of lesser significance of said counting means comprising said block address, wherein a common bit is included in both said sector address and said block address.

20. The apparatus of Claim 19 wherein said at least one channel of digitized information is recorded in plural parallel data tracks, each data track having successive data blocks therein with said data blocks located in the same relative position in all of said data tracks, relative to said sector interval, containing the same block addresses from one data track to another; and said encoding means further includes distributing means for distributing consecutive ones of the generated data blocks to respective ones of said data tracks.

21. The apparatus of Claim 17 wherein said control signal generating means includes synchronizing pattern generating means for generating a control synchronizing pattern located at a predetermined position in said control signal.

22. The apparatus of Claim 21 wherein said control synchronizing pattern is located at the beginning portion of said control signal, such that the period of said control synchronizing pattern is equal to said sector interval.

23. The apparatus of Claim 17 wherein said encoding means includes means for generating a data synchronizing signal in advance of said block address, such that the period of said data synchronizing signal is equal to the interval defined by a data block.

24. The apparatus of Claim 17 wherein said encoding means is selectively operative to encode said at least one channel of digitized information in one of plural formats;
and wherein said control signal generating means includes means for generating format identification data for identifying the selected format in which said at least one channel of digitized information is encoded, and means for adding said format identification signal to the control signal which is recorded