CA1187969A - Digital loop transceiver for interfacing a digital pabx to a digital subscriber set via a subscriber line - Google Patents
Digital loop transceiver for interfacing a digital pabx to a digital subscriber set via a subscriber lineInfo
- Publication number
- CA1187969A CA1187969A CA000414134A CA414134A CA1187969A CA 1187969 A CA1187969 A CA 1187969A CA 000414134 A CA000414134 A CA 000414134A CA 414134 A CA414134 A CA 414134A CA 1187969 A CA1187969 A CA 1187969A
- Authority
- CA
- Canada
- Prior art keywords
- digital
- channel
- subscriber line
- transmit
- receive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
Abstract
DIGITAL LOOP TRANSCEIVER FOR INTERFACING
A DIGITAL PABX TO A DIGITAL SUBSCRIBER SET
VIA A SUBSCRIBER LINE
Abstract In a digital telephone system, a digital private automatic branch exchange (PABX) has a plurality of digital line cards for coupling the PABX to respective digital subscriber sets via subscriber lines. In each digital line card, a digital loop transceiver operates in a master mode to couple the digital data bus of the PABX
to the subscriber line via a subscriber line interface circuit in response to control signals provided by the PABX on the control bus thereof. In each digital subscriber set, a digital loop transceiver operates in a slave mode to couple the subscriber set to the subscriber line via a subscriber line interface circuit and to provide the several control signals required by the other components thereof. The digital loop transceivers provide communication on each of two communication channels, with the digital data words of the first channel being treated the same as the digital data words of the second channel.
A DIGITAL PABX TO A DIGITAL SUBSCRIBER SET
VIA A SUBSCRIBER LINE
Abstract In a digital telephone system, a digital private automatic branch exchange (PABX) has a plurality of digital line cards for coupling the PABX to respective digital subscriber sets via subscriber lines. In each digital line card, a digital loop transceiver operates in a master mode to couple the digital data bus of the PABX
to the subscriber line via a subscriber line interface circuit in response to control signals provided by the PABX on the control bus thereof. In each digital subscriber set, a digital loop transceiver operates in a slave mode to couple the subscriber set to the subscriber line via a subscriber line interface circuit and to provide the several control signals required by the other components thereof. The digital loop transceivers provide communication on each of two communication channels, with the digital data words of the first channel being treated the same as the digital data words of the second channel.
Description
DIGIT~L LOOP TRANSCEIVER FOR INTERY~CING
A ~IGITAL PABX TO A D]GITAL SUBSCRIBER SET
VIA A SVBSCF~IBEK LINE
Technical Field This invention relates generally to digital telephone systems and, more particularly, to a digital loop transceiver for use in a digital telephone system comprising a digital PABX and a plurality of digital subscriber sets.
Background Art When a voice call is made using a conventional analog subscriber set, only a small portion of the freqllency spectrum available on the typical subscriber line is utilized. During the development of distributed data processing systems, an effort was made to utiliæe the e~isting subscriber line network to facilitate communication oE the digital data used by such systems.
Various types of modulator/demodulator (modem) devices have been developed to take advantage of the latent capability of the subscriber line network to support digital data communication at data rates siqniicantly greater than that required for analog voice communication.
For e~ample, synchronous modems are commercially available which utilize the differential phase shift keyed (DPSK) modulation/demodulation technique to provide data communication at rates up to 9600 baud. However~ even in the digital private automatic branch exchanges (PABXs) which support intra-exchange communication of voice information in the form of digital PCM voice data words, the response characteristics of the several analog components of the typical analog line card used therein generally prevent reliable communication at higher ratesO
Several techniques have been proposed for providing ~3 ~ 3~
higher speed digital data communication between subscr:ibers through such PABXs. However, such proposals typically require the installation of additional pairs of subscriber lines to subscribers requiring the service ancl/or redesign/modification of the particular PABX to prGvide the capability to process the pure digital data words in a manner different from the digital PCM voice data words.
Summary of the Invention Accordingly, it is an object of the present invention to enable digital data words to be commul1icated at significantly higher speeds over the existing, installed base of subscriber lines, without any redesign or modi.fication whatsoever oc the conventional digital PABX.
In accordance with the present invention, the analog to digital eonversion function required to support voice communication in the digital PABX is transerred from the PABX to the subscriber set itself, by moving the conventional codec/filter from the analocl line card to the subscriber set, and by interfaceing the codec/filter and the PABX to the subseriber line via a pair of digital :Loop transeeivers (~LT) eonstrueted in aecordance with the present invention. The existing subscriber line is then converted from the typieal, relatively low speed analog :I.ink into a high speed data lin~ by providing, at both the subscriber and exchange ends, a subscriber line interface network which is responsive to the much higher frequellcies7 e.g. up to about 256 kHz, otherwise unavailable on the typical subscriber lineO
Once the subscriber set has been converted into a cligital form and the existing subscriber l:ine upgracdecd to a high speed data link in accordance with the present invent.ion, the digital PCM voice data words ancl associated signalling information for a single voice call will require only about half of the bandwidth available on the subscriber line. ~ccordingly, the preferred form of the DLT of the present invention simultaneously supports a second communication channelr with the digital data words and associated signalling information of the second channel being time multiplexed with the di~ital data words and signalling information of the Eirst channel. ~owever, as -far as the DLT is concerned, neither, either or both of these channels may carry PCM voice data words, depending upon the requirements of a given subscriberO
~rief Description of the Drawings Figure 1 is a block representation oE a private automatic branch exchange (P~BX) adapted in accordance with the present invention.
Figure 2 is a schematic diagram of an anal.og line card for use in the PABX of Figure 1.
Figure 3 is a digital line card constructed in accordance with the present invention Eor use in the PABX
o:E Figure l~
Figure 4 is a digital subscriber set constructed in accordance with the present invention to communicate over a subscriber line with the digital line card of Figure 3.
Figure 5 is a digital loop transceiver (DLT) constructed in accordance with the present invention for
A ~IGITAL PABX TO A D]GITAL SUBSCRIBER SET
VIA A SVBSCF~IBEK LINE
Technical Field This invention relates generally to digital telephone systems and, more particularly, to a digital loop transceiver for use in a digital telephone system comprising a digital PABX and a plurality of digital subscriber sets.
Background Art When a voice call is made using a conventional analog subscriber set, only a small portion of the freqllency spectrum available on the typical subscriber line is utilized. During the development of distributed data processing systems, an effort was made to utiliæe the e~isting subscriber line network to facilitate communication oE the digital data used by such systems.
Various types of modulator/demodulator (modem) devices have been developed to take advantage of the latent capability of the subscriber line network to support digital data communication at data rates siqniicantly greater than that required for analog voice communication.
For e~ample, synchronous modems are commercially available which utilize the differential phase shift keyed (DPSK) modulation/demodulation technique to provide data communication at rates up to 9600 baud. However~ even in the digital private automatic branch exchanges (PABXs) which support intra-exchange communication of voice information in the form of digital PCM voice data words, the response characteristics of the several analog components of the typical analog line card used therein generally prevent reliable communication at higher ratesO
Several techniques have been proposed for providing ~3 ~ 3~
higher speed digital data communication between subscr:ibers through such PABXs. However, such proposals typically require the installation of additional pairs of subscriber lines to subscribers requiring the service ancl/or redesign/modification of the particular PABX to prGvide the capability to process the pure digital data words in a manner different from the digital PCM voice data words.
Summary of the Invention Accordingly, it is an object of the present invention to enable digital data words to be commul1icated at significantly higher speeds over the existing, installed base of subscriber lines, without any redesign or modi.fication whatsoever oc the conventional digital PABX.
In accordance with the present invention, the analog to digital eonversion function required to support voice communication in the digital PABX is transerred from the PABX to the subscriber set itself, by moving the conventional codec/filter from the analocl line card to the subscriber set, and by interfaceing the codec/filter and the PABX to the subseriber line via a pair of digital :Loop transeeivers (~LT) eonstrueted in aecordance with the present invention. The existing subscriber line is then converted from the typieal, relatively low speed analog :I.ink into a high speed data lin~ by providing, at both the subscriber and exchange ends, a subscriber line interface network which is responsive to the much higher frequellcies7 e.g. up to about 256 kHz, otherwise unavailable on the typical subscriber lineO
Once the subscriber set has been converted into a cligital form and the existing subscriber l:ine upgracdecd to a high speed data link in accordance with the present invent.ion, the digital PCM voice data words ancl associated signalling information for a single voice call will require only about half of the bandwidth available on the subscriber line. ~ccordingly, the preferred form of the DLT of the present invention simultaneously supports a second communication channelr with the digital data words and associated signalling information of the second channel being time multiplexed with the di~ital data words and signalling information of the Eirst channel. ~owever, as -far as the DLT is concerned, neither, either or both of these channels may carry PCM voice data words, depending upon the requirements of a given subscriberO
~rief Description of the Drawings Figure 1 is a block representation oE a private automatic branch exchange (P~BX) adapted in accordance with the present invention.
Figure 2 is a schematic diagram of an anal.og line card for use in the PABX of Figure 1.
Figure 3 is a digital line card constructed in accordance with the present invention Eor use in the PABX
o:E Figure l~
Figure 4 is a digital subscriber set constructed in accordance with the present invention to communicate over a subscriber line with the digital line card of Figure 3.
Figure 5 is a digital loop transceiver (DLT) constructed in accordance with the present invention for
2~ use in the digital line card of Figure 3 and the digital subscriber set of Figure 4~
Figure 6 is a schematic representation oE a 4-wire comrnunication system between the DLT in the digital line card of Figure 3 and the DLT in the digital subscriber set of Figure 4~
Figure 7 is a timing diagram illustrating a typical exchan~e between the DLT in the digital line card of Figure 3 and the PABX oE Figure 1.
Figure 8 is a timing diagram illustrating a typical exchange between the DLT in the subscriber set of Figure 4 and the codec/filter therein.
Figure 9 is a schematic representation o.. a 2~wire communication system between l:he DLT in the digital line carc1 of Figure 3 and the Dl,T in the diyital subscriber set o~ Ficiure 4.
Description of the Preferred Embodiment Shown in Figure 1 is a conventional private automatic branch exchange (PABX) 10 cornprised generally of a main 1n call processor 12 having associated memory 1~, a time slot intercl1ange circuit 16, a set of call processing microprocessors 18-18', each having an associated memory 20-2n', and a plurality of conventional analog line cards 22G In the illustrated form, the PABX 10 also includes at least two digital line cards 22' constructed in accordance with the present i.nvention.
In a typical digital telephone switching system such as the PAHX 10, the main call processor 12 coordinates, via a system bus 2~, the call processing activities of each of the several call processing microprocessors 18-18'. In turn, each of the call processing microprocessors 18-189 controls, via respective control buses 26-26', the communication of digital PCM voice data words via respective data buses 28-28' between the several line cards 22 assigned to such microprocessor 18-13'~
In general, each of the analog line cards 22 comprises a time slot assignment and control circuit (TSAC~ 30 for selectively enabling a codec/filter 32 to digitally encode an analog voice input signal received via a subscriber line interEace circuit (SLIC) 34 ~rom a conventional single channel subscriber set (not shown) coupled to tip and rinCJ conductors for output as a digital pulse code modulation (PCM) voice data word on the respective data bus 28-28', and to decode a digital PCM voice data word received on the data bus 28-28' for output as an analog voice output signal to the subscriber set (not shown) via the Sl,IC 3~. Shown in Figure 2 is a circuit schematic for such a conventional analog line card 22, usin~ components commercially available ~rom Motorola. The various control and data signals which are provided to or by the line card 22 are generally referred to as the "bac~splane" of the PABX 10.
In a typical telephone call initiated by a subscriber served by a "source" line card 22 controlled by, say, the call processing microprocessor 18 to a subscriber served by a "destination" line card 22 controlled by, for example, the ca].l processing microprocessor lB', the TS~C
30 on the source line card 22 initially detects via the associated SLIC 3~ that the source subscriber set is oFf hook/ and routes the call routing information to the call processing microprocessor 18 .~or transfer to the main call processor 12. If the destination line card 22 is not indicated in the mernory 1~ as being busy, the main call processor 12 then requests the call processing microprocessor 18' to notify the destination line card 22 of the call. If, upon providing the system-generated riny signal to the destination suhscri.ber set via the respective SLIC 3~, the associated TSAC 30 advises the call processor 18' that the destination subscriber set has been taken oEf hook, the call processing microprocessor 18' advises the main call processor 12 that the requested connection has been established. nuring a particular transmit time slot assigned by the main call processor 12, the TSAC 30 on the source line card 22 enables the associated codec/filter 32 to encode the analog voice signal then being received from the source subscriber set via the SLIC 34 for output as a digital PCM voice data word onto the data bus 28. Meanwhile, the main call processor 12 has enabled the time slot interchange circuit 16 to couple the data bus 28 to the data bus 28' to ~acil i~ate the requested intra~2a~change comm~nica~ n of the dig ita.lL PC:~ voice data word ~ Simultaneously~, ~he TSAC
30 on ~che destination line card 22 enables ~he associated co~ec,~filter 32 ~o decode the digi~al PC~q voice a~ata word 5 on che data bus 28 ' for output as an analog voice signal to the destinatiDn subscriber set via the S~C 3~0 In ~imi:lar manner~ ~ut during a different receive ~ime ~lot assigned by the main call processor 12, the descillhtion line card 2~ is allowed to enc~Dde th~ analog voie~e signal ~1 iD received rorn the d~stination subscriber se~ :~or ~ransmission as a dig i~al RCM voice da~a w~rd via data bu 2B ' i. interchange circuit î 6 and dal:a bus 28 to the source line card 22 for decoding and output to tlhe sollrce subscrlber ~et. If this exchange of digital ~CQ~ voice ~5 data words occurs at a sufficiently high :iFrarne rate, say o the order of 83c~z~ then it will appear to each of the ~subscriber~ that there is a direct analog :link between ~heir respective subscriber sets.
In the general form shown in ~igure 1~ each o:~ the ~?o digi~al line cards 22' comprises a time slot assignment and control circuit ~TSAC) 30 t for selectively enabling a s3ig ital loop tranceiver (DLT) 36 (see Figure 5 j ~o receive di~ita:l data word~ via a sub~criber line in~erface network
Figure 6 is a schematic representation oE a 4-wire comrnunication system between the DLT in the digital line card of Figure 3 and the DLT in the digital subscriber set of Figure 4~
Figure 7 is a timing diagram illustrating a typical exchan~e between the DLT in the digital line card of Figure 3 and the PABX oE Figure 1.
Figure 8 is a timing diagram illustrating a typical exchange between the DLT in the subscriber set of Figure 4 and the codec/filter therein.
Figure 9 is a schematic representation o.. a 2~wire communication system between l:he DLT in the digital line carc1 of Figure 3 and the Dl,T in the diyital subscriber set o~ Ficiure 4.
Description of the Preferred Embodiment Shown in Figure 1 is a conventional private automatic branch exchange (PABX) 10 cornprised generally of a main 1n call processor 12 having associated memory 1~, a time slot intercl1ange circuit 16, a set of call processing microprocessors 18-18', each having an associated memory 20-2n', and a plurality of conventional analog line cards 22G In the illustrated form, the PABX 10 also includes at least two digital line cards 22' constructed in accordance with the present i.nvention.
In a typical digital telephone switching system such as the PAHX 10, the main call processor 12 coordinates, via a system bus 2~, the call processing activities of each of the several call processing microprocessors 18-18'. In turn, each of the call processing microprocessors 18-189 controls, via respective control buses 26-26', the communication of digital PCM voice data words via respective data buses 28-28' between the several line cards 22 assigned to such microprocessor 18-13'~
In general, each of the analog line cards 22 comprises a time slot assignment and control circuit (TSAC~ 30 for selectively enabling a codec/filter 32 to digitally encode an analog voice input signal received via a subscriber line interEace circuit (SLIC) 34 ~rom a conventional single channel subscriber set (not shown) coupled to tip and rinCJ conductors for output as a digital pulse code modulation (PCM) voice data word on the respective data bus 28-28', and to decode a digital PCM voice data word received on the data bus 28-28' for output as an analog voice output signal to the subscriber set (not shown) via the Sl,IC 3~. Shown in Figure 2 is a circuit schematic for such a conventional analog line card 22, usin~ components commercially available ~rom Motorola. The various control and data signals which are provided to or by the line card 22 are generally referred to as the "bac~splane" of the PABX 10.
In a typical telephone call initiated by a subscriber served by a "source" line card 22 controlled by, say, the call processing microprocessor 18 to a subscriber served by a "destination" line card 22 controlled by, for example, the ca].l processing microprocessor lB', the TS~C
30 on the source line card 22 initially detects via the associated SLIC 3~ that the source subscriber set is oFf hook/ and routes the call routing information to the call processing microprocessor 18 .~or transfer to the main call processor 12. If the destination line card 22 is not indicated in the mernory 1~ as being busy, the main call processor 12 then requests the call processing microprocessor 18' to notify the destination line card 22 of the call. If, upon providing the system-generated riny signal to the destination suhscri.ber set via the respective SLIC 3~, the associated TSAC 30 advises the call processor 18' that the destination subscriber set has been taken oEf hook, the call processing microprocessor 18' advises the main call processor 12 that the requested connection has been established. nuring a particular transmit time slot assigned by the main call processor 12, the TSAC 30 on the source line card 22 enables the associated codec/filter 32 to encode the analog voice signal then being received from the source subscriber set via the SLIC 34 for output as a digital PCM voice data word onto the data bus 28. Meanwhile, the main call processor 12 has enabled the time slot interchange circuit 16 to couple the data bus 28 to the data bus 28' to ~acil i~ate the requested intra~2a~change comm~nica~ n of the dig ita.lL PC:~ voice data word ~ Simultaneously~, ~he TSAC
30 on ~che destination line card 22 enables ~he associated co~ec,~filter 32 ~o decode the digi~al PC~q voice a~ata word 5 on che data bus 28 ' for output as an analog voice signal to the destinatiDn subscriber set via the S~C 3~0 In ~imi:lar manner~ ~ut during a different receive ~ime ~lot assigned by the main call processor 12, the descillhtion line card 2~ is allowed to enc~Dde th~ analog voie~e signal ~1 iD received rorn the d~stination subscriber se~ :~or ~ransmission as a dig i~al RCM voice da~a w~rd via data bu 2B ' i. interchange circuit î 6 and dal:a bus 28 to the source line card 22 for decoding and output to tlhe sollrce subscrlber ~et. If this exchange of digital ~CQ~ voice ~5 data words occurs at a sufficiently high :iFrarne rate, say o the order of 83c~z~ then it will appear to each of the ~subscriber~ that there is a direct analog :link between ~heir respective subscriber sets.
In the general form shown in ~igure 1~ each o:~ the ~?o digi~al line cards 22' comprises a time slot assignment and control circuit ~TSAC) 30 t for selectively enabling a s3ig ital loop tranceiver (DLT) 36 (see Figure 5 j ~o receive di~ita:l data word~ via a sub~criber line in~erface network
3~ ~rDm ~ dllal channel~ digital ~ubscriber set~ ~;uch as .~5 that ~hown in Figure 4, which is collpled to respective receive and transmit pairs of tip and ring conductors~ ~or direc~E outpui~ on the respective lata bus 28~28 ~ :in the same manner ~s the digital PCM voice data WOrd5 are outp~t by the codec~iEilter 32 in the analog line cards 2;~!J and to 30 receiYe dig ital data wc>rds on the data bus ;~3 28 i ~or direct C>lltpllt to the subscriber ~;et via the subscriber li ne interface network 38 ,. Shown in Figure 3 is a c:ircuit ~chematic :Eor 'che dig ital 1 ine card 22 ', where.in: the TSAC
30 ' comprises a pair of the Motorola time slot a~;~ignment 3S oircuits (TSACs~, one for each of the 'cwo digltal communication channels the digital line card 22' is capable of simultaneously supporting; the DLT 36 comprises an integrated circuit constructed in accordance with Figure 5; and the subscriber line interface network 38 5 compri.ses a transmit isolation transformer 40 coupled to the tip and ring conductors which cornprise the receive pair of the subscriber line and a receive isolation transformer 42 coupled to the tip and ring conductors which comprise the transmit pair of the subscriber line.
As illustrated in Figure 3, the digital line card 22' responds to and provides the same contro:l and data signals which are provided to or by the anal.og line carcl 22 via the backplane of the PABX 10.
Shown in Figure 4 is a dual channel, diyital subscriber set 44 constructed in accordance with the present invention. In general, the subscriber set 4~1 comprises a digita.l loop transceiver (DLT) 36' (see Figure 5) for receiving digital data words Erom the digi.tal line card 22' (see E'igure 3) via a subscriber li.ne interface network 38' coupled to respective receive and transmit pairs of tip and ring conductors, for output, if digital PCM voice data words, to a conventional codec/filter 32' for subsequent decoding and output as an analog voice output via a voice I/O network 46, or, if digital data wordsl to a subscriber data processor (not shown) via a data port ~8, and for transmi ting digital data words provided either by the codec/filter 32' in the form of digital PCM
voice data words or by the subscriber data processor in the form of digital data words, to the digital line card 22' via the subscriber line interface network 3~ 7 O In the preEerred form, the voice I/O network 46 includes a voice input portion 50, and a voice output portion 52; the DLT
36' comprises an integrated circuit constructed in accorc3ance with Figure 5; and the subscriber line interface network 38' comprises a transmit isolation ~ 7~ ~7 transformer 40' coupled to the tip and ring conduccors ~hich comprise the transmit pair of the subscriber line and a receive isolation transfor~ner 42' coupled to the tip and ring conductors which comprise the receive pair of the subscriber lineO In the illustrated form~ a conventional tone generator 54 7 such as th~e Mostek MK5087, interacts with a dial keypad 56 and the voice I/O network 46 to provide the call routing infoemation required to establish each of the two communication channels, while a conventional hook switch 58 provides call initiation signalling information to the DLT 36l. An audible indication of an incoming call is provided via a ringing transducer 60. A subscriber set power supply 62 derives operating power for the several components o~ the subscriber set 4~1 from the subscriber line in a conventional manner.
Shown in Figure 5 is a block diagram oE the digital loop transceiver (DLT) 36, constructed in accordance with the present invention. In general~ the D:LT 36 comprises a digital interface portion 64 for interfacing with the PABX
lO in a master operating mode and with the coclec/filter 32 and subscriber data processor in a slave operating 1node, a modulator/demodulator portion 66 for transmitting and receiving digital data words via the subscriber line, and a sequencer and control portion 68 for controlliny the sequence of operations performed by the digital i.nterface and modulator/demodulator portions 64 and 66, respectively.
In the digital interface portion 64, a receive (RX) control circuit 70 responds to either o-f two channel receive enable signals, RE1 and RE2, by enabling a receive (RX) register 72 of the shift register type to serially receive digital clata bits via a receive (RX) terminal in synchronization with a receive data clock (R~C) on a CLK/RDC terminal. When a predetermined "frame" of data 't3~i~
(see discussion belo~) has been received, the sequencer and control portion 68 enables the RX register 72 to transfer the "transmit" frame of data in parallel into a transmitter (XMIT) register 74 in the modulator/
demodulator portion 66. Simu:ltaneously, the then-current states of the two channel signalli.ng bits on respective S1I and S2I terminals are latched and inserted into the frame of data in the XMIT reg:ister 74. Substantially independently, the sequencer and control portion 68 enables a transmit ~TX) register 76 to receive a "receive"
frame of data in parallel from a receiver (RCV) register 78 in the modulator/demodulator portion 660 Simultaneously, the two channel signalling bi.ts in the receive frame of data are latched and outputted on respective S10 and S20 terminals. In response to either o:E two channel transmit enable si.~nals, TEI and TE2, a transmit (TX) control circuit 80 enables the TX register 76 to serially transmit the receive frame oE data via a TX
terminal in synchronization with a transmit data clock (TDC) on an X1/TDC terminal.
In the modulator/demodulator portion 66, a digital to ana1og converter (DAC) control circuit 82 periodically enables a digital to analog converter (DAC) 84 to transmit the transmit frame of data in the XMIT reg.ister 74 to the ransmit transformer 40 in the subscriber line interface network 38 using a differential pair of output drivers 86 and 88 coupled to respective line output terminals I.01 and L02. In the preferred embodiment, the DAC 84 utilizes a burst differential phase shift keyed (DPS~) modulation technique at a carrier frequency of 256 kH~.
Substantially independently, an input buffer 90 oE the differential to single ended output type in the modulation/demodulation portion 66 couples the signal received from the receive transformer 42 in the subscriber line interface network 38 via line input terminals 1,I1 and - ~o -LT2 to a sync detector 92 via a window detector 94 and to a correlator 96 via a comparator 98. AS phase shits of -~he proper form are decoded by the correlakor 96, the ~decoded" bits are ~hifted into a shift register portion S -thereof which main~ains the most recently r2ceived set of da~a bits which might constitute a frame~ When ~he energy of a DPSK signal oP the proper frame length is detected~
the sync detector 92 provides a valid sync signal to enable the correlator 96 to transfer the receive ~rame of da~a bits being maintained thereing in parallel to the RCV register 78~ A demodulator having a sync de~ec~or and correlator of suitable form is shown and d~ribed in cope~ding Patent Application Serial No~ 416,611 filed Nov3mber 29, 198~. A
swi~ched oapacitor bandgap reference 100 similar to that shown and described in copending Patent Appllcation Sexial N~. 393,348 Eiled January 12, 1982 provides a precision reference voltage ~o the ~AC 84, the window detector 94, and the comparat~r 98 Periodically, the offsets of the input bu:Efer 900 the window detector 94, the comparator 98, and the ~andgap ~0 reference 100 are zeroed by an auto-zero circuit 102 in a manner ~imilar to that shown and described in copend.ing Paten-t Application Serial No. 393,980 filed January 12/ 1982u In operation, the DLT 36 provides duplex comm~nication of digi~al data words on a pair of independent channels 2~ and a signalling bit associated with each of the channels, between the duplex subscriber line and a digital data port. In a typical line transmission operation~ the RX
register 72 successively receives a digital data wcrd for each of the channels in synchronization with the receive data clock/ wlth the digital data word Eor the first of the channels being received from the ~igital I~O port via t~e RX terminal in response to the first o~ the channel r~ceive ena~le signals~ RE1, and the digital data ~ord for ~e secon~ cf the channels being received from the digital I/0 port via the RX terminal in response to the second of the channel receive enable signals, RE2. After the last data bit of the frame has been clocked into the ~X
register 72, both data words are transferred to the XMIT
register 7~, and the then-current states of the respective channe~ signalling bits on the S1I and S2I te-rmina]s added to complete the frame. As soon as the frarne has been assembled, the D~C control circuit 8~ actuates the DAC 84 to serially modulate the first and second digital data words and the respective channel signalling bits in the frame, for transmission via the transmit transformer ~0 to one of the pairs of wires in the subscriber lineO
In a typical line reception operation, the sync detector 92 monitors the signal received via the receive transEormer ~2 on the other pair of wires in the subscriber line, and provides a valid sync signal in response to detecting the energy of a DPSK modulated signal of the proper frame length. Meanwhile, the correlator 96 has been serially demodulatiny the ~0 sequentially received bits which might constitute a frame containing a digital data word for each of the channels and the respective channel signalling bits. In response to the valid sync signal, indicating that a valid frame has indeed been received, the correlator 96 transfers the ~5 frame to the RCVR register 78. At an appropriate time depending upon the mode of operation, the Erame is then transferred from the RCVR register 7~ to the TX register 7~ and the respective channel signalling bits latched for output on the S10 and S20 terminals. The TX register 7 then sequentially transmits the digital data words in s~nchronization with the transmit data clock, with the digital data word for the first channel being transmitted to the diyital I/0 port via the TX terminal in response to the first of the channel transmit enable signals, TE1, and the digital data word for the second channel being transmitted to the digital I/0 port via the rrx terminal in response to the second of the channel transmit enable signals, TE2.
Shown in Figure 6 is a schematic representation of a
30 ' comprises a pair of the Motorola time slot a~;~ignment 3S oircuits (TSACs~, one for each of the 'cwo digltal communication channels the digital line card 22' is capable of simultaneously supporting; the DLT 36 comprises an integrated circuit constructed in accordance with Figure 5; and the subscriber line interface network 38 5 compri.ses a transmit isolation transformer 40 coupled to the tip and ring conductors which cornprise the receive pair of the subscriber line and a receive isolation transformer 42 coupled to the tip and ring conductors which comprise the transmit pair of the subscriber line.
As illustrated in Figure 3, the digital line card 22' responds to and provides the same contro:l and data signals which are provided to or by the anal.og line carcl 22 via the backplane of the PABX 10.
Shown in Figure 4 is a dual channel, diyital subscriber set 44 constructed in accordance with the present invention. In general, the subscriber set 4~1 comprises a digita.l loop transceiver (DLT) 36' (see Figure 5) for receiving digital data words Erom the digi.tal line card 22' (see E'igure 3) via a subscriber li.ne interface network 38' coupled to respective receive and transmit pairs of tip and ring conductors, for output, if digital PCM voice data words, to a conventional codec/filter 32' for subsequent decoding and output as an analog voice output via a voice I/O network 46, or, if digital data wordsl to a subscriber data processor (not shown) via a data port ~8, and for transmi ting digital data words provided either by the codec/filter 32' in the form of digital PCM
voice data words or by the subscriber data processor in the form of digital data words, to the digital line card 22' via the subscriber line interface network 3~ 7 O In the preEerred form, the voice I/O network 46 includes a voice input portion 50, and a voice output portion 52; the DLT
36' comprises an integrated circuit constructed in accorc3ance with Figure 5; and the subscriber line interface network 38' comprises a transmit isolation ~ 7~ ~7 transformer 40' coupled to the tip and ring conduccors ~hich comprise the transmit pair of the subscriber line and a receive isolation transfor~ner 42' coupled to the tip and ring conductors which comprise the receive pair of the subscriber lineO In the illustrated form~ a conventional tone generator 54 7 such as th~e Mostek MK5087, interacts with a dial keypad 56 and the voice I/O network 46 to provide the call routing infoemation required to establish each of the two communication channels, while a conventional hook switch 58 provides call initiation signalling information to the DLT 36l. An audible indication of an incoming call is provided via a ringing transducer 60. A subscriber set power supply 62 derives operating power for the several components o~ the subscriber set 4~1 from the subscriber line in a conventional manner.
Shown in Figure 5 is a block diagram oE the digital loop transceiver (DLT) 36, constructed in accordance with the present invention. In general~ the D:LT 36 comprises a digital interface portion 64 for interfacing with the PABX
lO in a master operating mode and with the coclec/filter 32 and subscriber data processor in a slave operating 1node, a modulator/demodulator portion 66 for transmitting and receiving digital data words via the subscriber line, and a sequencer and control portion 68 for controlliny the sequence of operations performed by the digital i.nterface and modulator/demodulator portions 64 and 66, respectively.
In the digital interface portion 64, a receive (RX) control circuit 70 responds to either o-f two channel receive enable signals, RE1 and RE2, by enabling a receive (RX) register 72 of the shift register type to serially receive digital clata bits via a receive (RX) terminal in synchronization with a receive data clock (R~C) on a CLK/RDC terminal. When a predetermined "frame" of data 't3~i~
(see discussion belo~) has been received, the sequencer and control portion 68 enables the RX register 72 to transfer the "transmit" frame of data in parallel into a transmitter (XMIT) register 74 in the modulator/
demodulator portion 66. Simu:ltaneously, the then-current states of the two channel signalli.ng bits on respective S1I and S2I terminals are latched and inserted into the frame of data in the XMIT reg:ister 74. Substantially independently, the sequencer and control portion 68 enables a transmit ~TX) register 76 to receive a "receive"
frame of data in parallel from a receiver (RCV) register 78 in the modulator/demodulator portion 660 Simultaneously, the two channel signalling bi.ts in the receive frame of data are latched and outputted on respective S10 and S20 terminals. In response to either o:E two channel transmit enable si.~nals, TEI and TE2, a transmit (TX) control circuit 80 enables the TX register 76 to serially transmit the receive frame oE data via a TX
terminal in synchronization with a transmit data clock (TDC) on an X1/TDC terminal.
In the modulator/demodulator portion 66, a digital to ana1og converter (DAC) control circuit 82 periodically enables a digital to analog converter (DAC) 84 to transmit the transmit frame of data in the XMIT reg.ister 74 to the ransmit transformer 40 in the subscriber line interface network 38 using a differential pair of output drivers 86 and 88 coupled to respective line output terminals I.01 and L02. In the preferred embodiment, the DAC 84 utilizes a burst differential phase shift keyed (DPS~) modulation technique at a carrier frequency of 256 kH~.
Substantially independently, an input buffer 90 oE the differential to single ended output type in the modulation/demodulation portion 66 couples the signal received from the receive transformer 42 in the subscriber line interface network 38 via line input terminals 1,I1 and - ~o -LT2 to a sync detector 92 via a window detector 94 and to a correlator 96 via a comparator 98. AS phase shits of -~he proper form are decoded by the correlakor 96, the ~decoded" bits are ~hifted into a shift register portion S -thereof which main~ains the most recently r2ceived set of da~a bits which might constitute a frame~ When ~he energy of a DPSK signal oP the proper frame length is detected~
the sync detector 92 provides a valid sync signal to enable the correlator 96 to transfer the receive ~rame of da~a bits being maintained thereing in parallel to the RCV register 78~ A demodulator having a sync de~ec~or and correlator of suitable form is shown and d~ribed in cope~ding Patent Application Serial No~ 416,611 filed Nov3mber 29, 198~. A
swi~ched oapacitor bandgap reference 100 similar to that shown and described in copending Patent Appllcation Sexial N~. 393,348 Eiled January 12, 1982 provides a precision reference voltage ~o the ~AC 84, the window detector 94, and the comparat~r 98 Periodically, the offsets of the input bu:Efer 900 the window detector 94, the comparator 98, and the ~andgap ~0 reference 100 are zeroed by an auto-zero circuit 102 in a manner ~imilar to that shown and described in copend.ing Paten-t Application Serial No. 393,980 filed January 12/ 1982u In operation, the DLT 36 provides duplex comm~nication of digi~al data words on a pair of independent channels 2~ and a signalling bit associated with each of the channels, between the duplex subscriber line and a digital data port. In a typical line transmission operation~ the RX
register 72 successively receives a digital data wcrd for each of the channels in synchronization with the receive data clock/ wlth the digital data word Eor the first of the channels being received from the ~igital I~O port via t~e RX terminal in response to the first o~ the channel r~ceive ena~le signals~ RE1, and the digital data ~ord for ~e secon~ cf the channels being received from the digital I/0 port via the RX terminal in response to the second of the channel receive enable signals, RE2. After the last data bit of the frame has been clocked into the ~X
register 72, both data words are transferred to the XMIT
register 7~, and the then-current states of the respective channe~ signalling bits on the S1I and S2I te-rmina]s added to complete the frame. As soon as the frarne has been assembled, the D~C control circuit 8~ actuates the DAC 84 to serially modulate the first and second digital data words and the respective channel signalling bits in the frame, for transmission via the transmit transformer ~0 to one of the pairs of wires in the subscriber lineO
In a typical line reception operation, the sync detector 92 monitors the signal received via the receive transEormer ~2 on the other pair of wires in the subscriber line, and provides a valid sync signal in response to detecting the energy of a DPSK modulated signal of the proper frame length. Meanwhile, the correlator 96 has been serially demodulatiny the ~0 sequentially received bits which might constitute a frame containing a digital data word for each of the channels and the respective channel signalling bits. In response to the valid sync signal, indicating that a valid frame has indeed been received, the correlator 96 transfers the ~5 frame to the RCVR register 78. At an appropriate time depending upon the mode of operation, the Erame is then transferred from the RCVR register 7~ to the TX register 7~ and the respective channel signalling bits latched for output on the S10 and S20 terminals. The TX register 7 then sequentially transmits the digital data words in s~nchronization with the transmit data clock, with the digital data word for the first channel being transmitted to the diyital I/0 port via the TX terminal in response to the first of the channel transmit enable signals, TE1, and the digital data word for the second channel being transmitted to the digital I/0 port via the rrx terminal in response to the second of the channel transmit enable signals, TE2.
Shown in Figure 6 is a schematic representation of a
4-wire or duplex subscriber line which has been coupled at the exchange end thereof to the DLT 36 in the digital line card 22' via the transmit and receive transEormers 40 and 42, respectively, and at the subscriber end thereof to the DLT 36~ in the digital subscriber set 44 via -the transmit ar.d receive transformers 40' and 42', respectively In the dual-channel form of the duplex system, a frame of data comprises an 8-bit d:igital data word for the first channel, an 8-bit diyital data word for the second channel, and the signalling bits for the :~irst and second channels. PreEerably, the frame also includes a parity bit, either even or odd, as desired. A suitable frame ~ormat is illustrated in Figure 6.
In the digital line card 22' shown in Figure 3, the DLT
36 is placed in the master mode of operatlon by a logic high signal on a master/slave (M/S) terminal. :tn the master mode, the DL.T 36 emulates the codec/filter 32 with respect to the backplane by receiving/transmitting the digital data words just like the codec/-Eilter 32, and by responding to the various control signals just li~e the codec/filter 32. In particular, the RX register 72 successively receives a digital data word for each of the channels in synchroniza-tion with the data clock provided by the PABX 10 via the backplane, with the data word for -the first channel being received from the backplane via the RX termi.nal in response to the REl signal provided by a respective one of the TSACs 30 during the receive time slot assigned to the first channel~ and the data word for the second channel being received from the backplane via the RX terminal in response to the RE2 signal provided by the other TSAC 30 during the receive time slot assigned to the second channel. In response to the ne~t master sync inp~t (MSI) received via an X2./MSI terminal after the last data bit oE the frame has beerl clocked into the RX
register 72, both digital data words are transferred to the XMIT register 74, and the then-current states of the respective channel signalling bits provide~ via the S1I
and S2I terminals by the TSACs 30, respectivelyr added to complete the frame. As soon as the ~rame has been assembled, the D~C control circuit 82 actuates the DAC 84 to serially modulate the first and second digit~l clata words and the respective channel signalling bits in the frame, for transmission via the transmit trans~ormer 40 to the receive pair of wires in the subscriber line.
Simultaneously, the sync detector 92 monitors the signal received via the receive transformer ~2 on the trans~it pair of wires in the subscriber line, and provides the valid sync siynal in response to detecting the energy oE a DPSK modulated signal o~ the proper frame ]ength. Meanwhile, the correlator 96 has been serially demodulating the sequentially received bits which might constitute a frame containing a digital data word for each of the channels and the respective channel siynalling bits. In response to the valid sync signal, indicating that a valid frame has indeed been received, the correlator 96 transfers the frame to the RCVR register 78.
In response to the next MSI, the frame is then transferred ~rom the RC~R register 78 to the TX register 76 and the respective chaannel siynalling bits latched for output on the S10 and S20 terminals. The TX register 76 then sequentially transmits the digital data words in synchronization with the transmit data clock provided by the PABX 10 via the backplane, with the digital data word for the ~irst channel being transmitted to the backplane via the TX terminal in response to the TE1 signal provided by the first one of the TSACs 30 during the transmit time slot assigned to the first channel, and the digital data word for the second data channel being transmitted tv the backplane via the TX terminal in response to the TE2 signal provided by the other TSAC 30 during the transmit time slot assigned to the second channel. A typical seyuential interaction of the DLT 36 with the TS~Cs 30, anc] with the PABX 10 is illustrated by way of example in the timing diagram oE Figure 70 In the subscriber set 44 shown in Figure 4, the DLT 36' is placec3 in the slave mode of operation by a logic low on the master/slave (M/S) terminal. In the slave mode, the DLT ~6l emulates the functions of the TSAC 30 and the backplane with respect to the codec/Eilter 32' by providing the digital PCM voice data words and control signais necessary for the codec/filter 32' to operate, and by receiving the digital PCM voice data worcls provided by the codec/filter 32' just like the backplane. In this mode~ the sync detector 92 monitors the sigr1a:L received via the receive transformer 42' on the receive pair of 2n wires in the subscriber line; and provides the valid sync signal in response to detecting the energy vE a DPSK
modulated signal of the proper frame lengthO Meanwhile, the correlator 96 has been serially demodulatinc3 the se~uentially received bits which might constitute a frame containing a digital data word Eor each of the channels and the respective channel signalling bits. In response to ti1e valid sync signal, indicating that a valid frame has indeed been received, the correlator 96 transfers -the frame to the RCVR register 78. The frame is then promptly transferred Erom the RCVR register 78 to the TX register 76 and the respective channel signalling bits latched Eor output on the S10 and S20 terminals. The TX register 76 then sequentially transmits the digital data words in synchronization with a transmit c]ata clock cJenerated by a prescaler anc3 oscillator 104 using a crystal cvupled between the X1/TDC and ~2/MSI terminals, with the dicJital da~a word for the first channel being transmitted to the coclec/fil-ter 32' via the TX terminal in synchroni~ation with a T~1 signal generated by the TX control 80 relative to the last valid sync signal, and the diyital data word for the second data channel being transmitted to the data port 48 via the TX terminal in synchroni~at:ion with a r~2 signal generated by the TX control 80 relative to the last valic1 sync signal.
In response to each of the valid sync siynals provided by the sync detector 92, the RX register 72 s~ccessively receives a digital data word for each of the channels in syrlchronization with a receive data clock generated by the sequencer and control 68, with the digital PCM voice data word Eor the first channel being received from the codec/fi.:Lter 32' via the RX terminal in synchronization with an RE1 signal generated by the RX control 70 relative to the last valid sync signal, and the digital data word Eor the second channel being received from the data port 48 via the RX terminal in response to an RE2 signal generated by the RX control 70 relative to the last valid sync signal. In response to the next valid sync signal provided by the sync detector 92, both digital data words are transferred to the XMIT register 74 and the then-current states of the respective channel signalling bits provided via the S1I and S2I terminals by the hook switch 58 and, if appropriate, the subscriber data processor, respectively, are added to complete the frame.
As soon as the frame has been assembled, the DAC control circuit 32 actuates the DAC 84 to serially modulate the first and second digital data words and the respective channel signalling bits in the frame, for transmission via -the transmit transEormer 40' to the transmit pair of wires in the subseriber line. A typical seyuential interaction of the DLT 36' with the codec/filter 32' and the subscriber data processor is i]lustrated by way of example in the timing diagram of Figure 8.
Although the DLT 36 is deslgned to operate primarily i.n the dual-channel mode over a duplex subsc:riber line, the DLT 36 may be operated in an exchange which has only one pair oE wires in each subscriber line by applying a logic high to a format (FOR) terminal thereof~ In the illustrated form of such a 2-wire system shown in Figure 9~ the halE duplex subscriber line is coupled at the exchange end thereof to the DLT 36 in the dlgital l.ine card 22' via a transmit/receive isolation transformer 106, and at the subscriber end thereof to the DLrr 36' in the digital subscriber set 44 via a transmit/~eceive isolation transformer 106'. In the dual-channel form of the half duplex system, a frame of data comprises an 8-bit digital data word Eor the first channel, the signalling bit for the firs-t channel, and a second sign211ing bit for use by the subscriber data processor as a digital data bit.
Preerably~ the frame also i.ncludes a parity bit, either even or odd, as desired. A suitable frame :Eormat is illustrated in Figure 9. Since only a single digital data bit may be transferred in each frame, the effective data bit transmission rate is only 8k~z rather than the 64k~z of the duplex system. However, this reducecl data rate may be acceptable in situations where the cost to install the second pair of wires in the subscriber line o~ltweighs the benefits of higher transmission rate.
These and other changes and modifications may be made in the arrangement OL- construction of the ~arious parts or 3Q elements of the preferred embodiments as disclosed herein ~ithout departing from the spirit and scope oF the present invention as defined in the appended claimsO
In the digital line card 22' shown in Figure 3, the DLT
36 is placed in the master mode of operatlon by a logic high signal on a master/slave (M/S) terminal. :tn the master mode, the DL.T 36 emulates the codec/filter 32 with respect to the backplane by receiving/transmitting the digital data words just like the codec/-Eilter 32, and by responding to the various control signals just li~e the codec/filter 32. In particular, the RX register 72 successively receives a digital data word for each of the channels in synchroniza-tion with the data clock provided by the PABX 10 via the backplane, with the data word for -the first channel being received from the backplane via the RX termi.nal in response to the REl signal provided by a respective one of the TSACs 30 during the receive time slot assigned to the first channel~ and the data word for the second channel being received from the backplane via the RX terminal in response to the RE2 signal provided by the other TSAC 30 during the receive time slot assigned to the second channel. In response to the ne~t master sync inp~t (MSI) received via an X2./MSI terminal after the last data bit oE the frame has beerl clocked into the RX
register 72, both digital data words are transferred to the XMIT register 74, and the then-current states of the respective channel signalling bits provide~ via the S1I
and S2I terminals by the TSACs 30, respectivelyr added to complete the frame. As soon as the ~rame has been assembled, the D~C control circuit 82 actuates the DAC 84 to serially modulate the first and second digit~l clata words and the respective channel signalling bits in the frame, for transmission via the transmit trans~ormer 40 to the receive pair of wires in the subscriber line.
Simultaneously, the sync detector 92 monitors the signal received via the receive transformer ~2 on the trans~it pair of wires in the subscriber line, and provides the valid sync siynal in response to detecting the energy oE a DPSK modulated signal o~ the proper frame ]ength. Meanwhile, the correlator 96 has been serially demodulating the sequentially received bits which might constitute a frame containing a digital data word for each of the channels and the respective channel siynalling bits. In response to the valid sync signal, indicating that a valid frame has indeed been received, the correlator 96 transfers the frame to the RCVR register 78.
In response to the next MSI, the frame is then transferred ~rom the RC~R register 78 to the TX register 76 and the respective chaannel siynalling bits latched for output on the S10 and S20 terminals. The TX register 76 then sequentially transmits the digital data words in synchronization with the transmit data clock provided by the PABX 10 via the backplane, with the digital data word for the ~irst channel being transmitted to the backplane via the TX terminal in response to the TE1 signal provided by the first one of the TSACs 30 during the transmit time slot assigned to the first channel, and the digital data word for the second data channel being transmitted tv the backplane via the TX terminal in response to the TE2 signal provided by the other TSAC 30 during the transmit time slot assigned to the second channel. A typical seyuential interaction of the DLT 36 with the TS~Cs 30, anc] with the PABX 10 is illustrated by way of example in the timing diagram oE Figure 70 In the subscriber set 44 shown in Figure 4, the DLT 36' is placec3 in the slave mode of operation by a logic low on the master/slave (M/S) terminal. In the slave mode, the DLT ~6l emulates the functions of the TSAC 30 and the backplane with respect to the codec/Eilter 32' by providing the digital PCM voice data words and control signais necessary for the codec/filter 32' to operate, and by receiving the digital PCM voice data worcls provided by the codec/filter 32' just like the backplane. In this mode~ the sync detector 92 monitors the sigr1a:L received via the receive transformer 42' on the receive pair of 2n wires in the subscriber line; and provides the valid sync signal in response to detecting the energy vE a DPSK
modulated signal of the proper frame lengthO Meanwhile, the correlator 96 has been serially demodulatinc3 the se~uentially received bits which might constitute a frame containing a digital data word Eor each of the channels and the respective channel signalling bits. In response to ti1e valid sync signal, indicating that a valid frame has indeed been received, the correlator 96 transfers -the frame to the RCVR register 78. The frame is then promptly transferred Erom the RCVR register 78 to the TX register 76 and the respective channel signalling bits latched Eor output on the S10 and S20 terminals. The TX register 76 then sequentially transmits the digital data words in synchronization with a transmit c]ata clock cJenerated by a prescaler anc3 oscillator 104 using a crystal cvupled between the X1/TDC and ~2/MSI terminals, with the dicJital da~a word for the first channel being transmitted to the coclec/fil-ter 32' via the TX terminal in synchroni~ation with a T~1 signal generated by the TX control 80 relative to the last valid sync signal, and the diyital data word for the second data channel being transmitted to the data port 48 via the TX terminal in synchroni~at:ion with a r~2 signal generated by the TX control 80 relative to the last valic1 sync signal.
In response to each of the valid sync siynals provided by the sync detector 92, the RX register 72 s~ccessively receives a digital data word for each of the channels in syrlchronization with a receive data clock generated by the sequencer and control 68, with the digital PCM voice data word Eor the first channel being received from the codec/fi.:Lter 32' via the RX terminal in synchronization with an RE1 signal generated by the RX control 70 relative to the last valid sync signal, and the digital data word Eor the second channel being received from the data port 48 via the RX terminal in response to an RE2 signal generated by the RX control 70 relative to the last valid sync signal. In response to the next valid sync signal provided by the sync detector 92, both digital data words are transferred to the XMIT register 74 and the then-current states of the respective channel signalling bits provided via the S1I and S2I terminals by the hook switch 58 and, if appropriate, the subscriber data processor, respectively, are added to complete the frame.
As soon as the frame has been assembled, the DAC control circuit 32 actuates the DAC 84 to serially modulate the first and second digital data words and the respective channel signalling bits in the frame, for transmission via -the transmit transEormer 40' to the transmit pair of wires in the subseriber line. A typical seyuential interaction of the DLT 36' with the codec/filter 32' and the subscriber data processor is i]lustrated by way of example in the timing diagram of Figure 8.
Although the DLT 36 is deslgned to operate primarily i.n the dual-channel mode over a duplex subsc:riber line, the DLT 36 may be operated in an exchange which has only one pair oE wires in each subscriber line by applying a logic high to a format (FOR) terminal thereof~ In the illustrated form of such a 2-wire system shown in Figure 9~ the halE duplex subscriber line is coupled at the exchange end thereof to the DLT 36 in the dlgital l.ine card 22' via a transmit/receive isolation transformer 106, and at the subscriber end thereof to the DLrr 36' in the digital subscriber set 44 via a transmit/~eceive isolation transformer 106'. In the dual-channel form of the half duplex system, a frame of data comprises an 8-bit digital data word Eor the first channel, the signalling bit for the firs-t channel, and a second sign211ing bit for use by the subscriber data processor as a digital data bit.
Preerably~ the frame also i.ncludes a parity bit, either even or odd, as desired. A suitable frame :Eormat is illustrated in Figure 9. Since only a single digital data bit may be transferred in each frame, the effective data bit transmission rate is only 8k~z rather than the 64k~z of the duplex system. However, this reducecl data rate may be acceptable in situations where the cost to install the second pair of wires in the subscriber line o~ltweighs the benefits of higher transmission rate.
These and other changes and modifications may be made in the arrangement OL- construction of the ~arious parts or 3Q elements of the preferred embodiments as disclosed herein ~ithout departing from the spirit and scope oF the present invention as defined in the appended claimsO
Claims (16)
1. A digital loop transceiver circuit for providing duplex communication of digital data words on first and second channels and a signalling bit associated with each of said first and second channels, between a duplex subscriber line and a digital 1/0 port, the transceiver circuit comprising:
receiver means for successively receiving a first and a second of said digital data words and of said signalling bits in synchronization with a receive data clock, said first digital data word and the respective signalling bit being received from said digital 1/0 port in response to a first channel receive enable signal, and said second digital data word and the respective signalling bit being received from said digital 1/0 port in response to a second channel receive enable signal;
modulation means for serially modulating said first and second digital data words and the respective signalling bits for transmission via a first portion of said subscriber line;
sync detection means for detecting a modulated signal on a second portion of said subscriber line, and providing a valid sync signal in response to said detection;
demodulation means for serially demodulating in response to said valid sync signal, a third and a fourth of said digital data words and of said signalling bits received via said second portion of said subscriber line; and transmitter means for transmitting said third and fourth digital data words and the respective signalling bits in synchronization with a transmit data clock, said third digital data word being transmitted to said digital 1/0 port in response to a first channel transmit enable signal, and said fourth digital data word being transmitted to said digital data port in response to a second channel transmit enable signal.
receiver means for successively receiving a first and a second of said digital data words and of said signalling bits in synchronization with a receive data clock, said first digital data word and the respective signalling bit being received from said digital 1/0 port in response to a first channel receive enable signal, and said second digital data word and the respective signalling bit being received from said digital 1/0 port in response to a second channel receive enable signal;
modulation means for serially modulating said first and second digital data words and the respective signalling bits for transmission via a first portion of said subscriber line;
sync detection means for detecting a modulated signal on a second portion of said subscriber line, and providing a valid sync signal in response to said detection;
demodulation means for serially demodulating in response to said valid sync signal, a third and a fourth of said digital data words and of said signalling bits received via said second portion of said subscriber line; and transmitter means for transmitting said third and fourth digital data words and the respective signalling bits in synchronization with a transmit data clock, said third digital data word being transmitted to said digital 1/0 port in response to a first channel transmit enable signal, and said fourth digital data word being transmitted to said digital data port in response to a second channel transmit enable signal.
2. A digital subscriber set having substantially indepen-dent voice and data channels, said digital subscriber set comprising:
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
data channel means for receiving a digital information input data word provided to said digital subscriber set, and for transmitting from said digital subscriber set a received digital information input data word;
signalling means for selectively generating call control signals, including a transmit channel signalling bit, for each of said voice and data channels, and for providing an output signal in response to receviving a predetermined receive channel signalling bit for each of said voice and data channels;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and the digital loop transceiver means of claim 1 coupled between said subscriber line interface means and said voice channel means, said data channel means and said signalling means wherein said digital PCM voice input data word, said digital information input data word, said digital PCM voice output data word, and said digital information output data word comprise said first, second, third and fourth digital data words, respectively, wherein said transmit channel sig-nalling bits comprise said first and second signalling bits, and wherein said receive channel signalling bits comprise said third and fourth signalling bits.
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
data channel means for receiving a digital information input data word provided to said digital subscriber set, and for transmitting from said digital subscriber set a received digital information input data word;
signalling means for selectively generating call control signals, including a transmit channel signalling bit, for each of said voice and data channels, and for providing an output signal in response to receviving a predetermined receive channel signalling bit for each of said voice and data channels;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and the digital loop transceiver means of claim 1 coupled between said subscriber line interface means and said voice channel means, said data channel means and said signalling means wherein said digital PCM voice input data word, said digital information input data word, said digital PCM voice output data word, and said digital information output data word comprise said first, second, third and fourth digital data words, respectively, wherein said transmit channel sig-nalling bits comprise said first and second signalling bits, and wherein said receive channel signalling bits comprise said third and fourth signalling bits.
3. A telecommunication subscriber line interface circuit for coupling a digital switching system having a digital data bus and a control bus via a duplex subscriber line to a digital subscriber set having time multiplexed first and second digital data channels, the interface circuit comprising:
time slot assignment and control means coupled to said control bus and responsive to control signals received therefrom and to first and second transmit channel signalling bits coupled thereto, for selectively providing first and second receive enable signals during respective first and second receive channel time slots, first and second transmit enable signals during respective first and second transmit channel time slots, and first and second receive channel signalling bits;
subscriber line interface means for coupling said inter-face circuit to a transmit and a receive portion of said duplex subscriber line; and the digital loop transcriver means of claim 1 coupled between said subscriber line interface means and said data bus, and to said time slot assignment and control means, wherein said first and second transmit channel signalling bits comprise said first and second signalling bits and wherein said first and second receive channel signalling bits comprise said third and fourth signalling bits.
time slot assignment and control means coupled to said control bus and responsive to control signals received therefrom and to first and second transmit channel signalling bits coupled thereto, for selectively providing first and second receive enable signals during respective first and second receive channel time slots, first and second transmit enable signals during respective first and second transmit channel time slots, and first and second receive channel signalling bits;
subscriber line interface means for coupling said inter-face circuit to a transmit and a receive portion of said duplex subscriber line; and the digital loop transcriver means of claim 1 coupled between said subscriber line interface means and said data bus, and to said time slot assignment and control means, wherein said first and second transmit channel signalling bits comprise said first and second signalling bits and wherein said first and second receive channel signalling bits comprise said third and fourth signalling bits.
4. A digital subscriber set having substantially indepen-dent voice and data channels, said digital subscriber set comprising:
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
data channel means for receiving a digital information input data word provided to said digital subscriber set, and for transmitting from said digital subscriber set a received digital information input data word;
signalling means for selectively generating call control signals, including a transmit channel signalling bit, for each of said voice and data channels, and for providing an output signal in response to receiving a predetermined receive channel signalling bit for each of said voice and data channels;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and digital loop transceiver means coupled between said subscriber line interface means and said voice channel means, said data channel means and said signalling means, comprising:
sync detection means for detecting a modulated signal on said transmit portion of said subscriber line via said sub-scriber line interface means, providing a valid sync signal in response to the detection thereof, and providing first and second receive enable signals and first and second transmit enable signals in predetermined relationship to said detection;
demodulation means for serially demodulating, in response to said valid sync signal, a digital PCM voice input data word and a digital output data word and a receive channel signalling bit associated with each, received from said transmit portion of said subscriber line via said subscriber line inter-face means;
transmitter means for transmitting said digital PCM voice output data word and said digital information input data word and the respective receive channel signalling bits in syn-chronization with a data clock developed by said transmitter means, said digital PCM voice output data word being transmitted to said voice channel means in response to said first transmit enable signal, said digital information input data word being transmitted to said data channel means in response to said second transmit enable signal, and said signalling bits being transmitted to said signalling means;
receiver means for successively receiving a digital PCM
voice input data word and a digital information input data word and a transmit channel signalling bit associated with each, in synchronization with said data clock, said digital PCM voice input data word being received from said voice channel means in response to said first receive enable signal, said digital information input data word being received from said data channel means in response to said second receive enable signal, and said transmit channel signalling bits being received from said signalling means; and modulation means for serially modulating said digital PCM voice input data word and said digital information input data word and the respective transmit channel signalling bits for transmission in response to said valid sync signal to said receive portion of said subscriber line via said subscriber line interface means.
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
data channel means for receiving a digital information input data word provided to said digital subscriber set, and for transmitting from said digital subscriber set a received digital information input data word;
signalling means for selectively generating call control signals, including a transmit channel signalling bit, for each of said voice and data channels, and for providing an output signal in response to receiving a predetermined receive channel signalling bit for each of said voice and data channels;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and digital loop transceiver means coupled between said subscriber line interface means and said voice channel means, said data channel means and said signalling means, comprising:
sync detection means for detecting a modulated signal on said transmit portion of said subscriber line via said sub-scriber line interface means, providing a valid sync signal in response to the detection thereof, and providing first and second receive enable signals and first and second transmit enable signals in predetermined relationship to said detection;
demodulation means for serially demodulating, in response to said valid sync signal, a digital PCM voice input data word and a digital output data word and a receive channel signalling bit associated with each, received from said transmit portion of said subscriber line via said subscriber line inter-face means;
transmitter means for transmitting said digital PCM voice output data word and said digital information input data word and the respective receive channel signalling bits in syn-chronization with a data clock developed by said transmitter means, said digital PCM voice output data word being transmitted to said voice channel means in response to said first transmit enable signal, said digital information input data word being transmitted to said data channel means in response to said second transmit enable signal, and said signalling bits being transmitted to said signalling means;
receiver means for successively receiving a digital PCM
voice input data word and a digital information input data word and a transmit channel signalling bit associated with each, in synchronization with said data clock, said digital PCM voice input data word being received from said voice channel means in response to said first receive enable signal, said digital information input data word being received from said data channel means in response to said second receive enable signal, and said transmit channel signalling bits being received from said signalling means; and modulation means for serially modulating said digital PCM voice input data word and said digital information input data word and the respective transmit channel signalling bits for transmission in response to said valid sync signal to said receive portion of said subscriber line via said subscriber line interface means.
5. A telecommunication subscriber line interface circuit for coupling a digital switching system having a digital data bus and a control bus via a duplex subscriber line to a digital subscriber set having time multiplexed first and second digital data channels, the interface circuit comprising:
time slot assignment and control means coupled to said control bus and responsive to control signals received therefrom and to first and second transmit channel signalling bits coupled thereto, for selectively providing first and second receive enable signals during respective first and second receive channel time slots, first and second transmit enable signals during respective first and second transmit channel time slots, and first and second receive channel signalling bits;
subscriber line interface means for coupling said inter-face circuit to a transmit and a receive portion of said duplex subscriber line; and digital loop transceiver means coupled between said sub-scriber line interface means and said data bus, and to said time slot assignment and control means, said transceiver com-prising:
receiver means for successively receiving first and second digital data words and the receive channel signalling bit associated with each in synchronization with a receive data clock provided by said switching system, said first digital data word being received from said data bus in response to said first receive enable signal, said second digital data word being received from said data bus in response to said second receive enable signal, and said receive channel signal-ling bits being received from said time slot assignment and control means;
modulation means for serially modulating said first and second digital data words and the respective receive channel signalling bits for transmission, in response to a sync signal provided by said switching system, to said transmit portion of said subscriber line via said subscriber line interface means;
sync detection means for detecting a modulated signal on said receive portion of said subscriber line via said subscriber line interface means; and for providing a valid sync signal in response to the detection thereof;
demodulation means for serially demodulating, in response to said valid sync signal, third and fourth digital data words and a transmit channel signalling bit associated with each, received on said receive portion of said subscriber line via said subscriber line interface means; and transmitter means for transmitting said third and fourth digital data words and the respective transmit channel signal-ling bits in synchronization with a transmit data clock provided by said switching system, said third digital data word being transmitted to said data bus in response to said first transmit enable signal, said second digital data word being transmitted to said data bus in response to said second transmit enable signal, and said transmit channel signalling bits being trans-mitted to said time slot assignment and control means.
time slot assignment and control means coupled to said control bus and responsive to control signals received therefrom and to first and second transmit channel signalling bits coupled thereto, for selectively providing first and second receive enable signals during respective first and second receive channel time slots, first and second transmit enable signals during respective first and second transmit channel time slots, and first and second receive channel signalling bits;
subscriber line interface means for coupling said inter-face circuit to a transmit and a receive portion of said duplex subscriber line; and digital loop transceiver means coupled between said sub-scriber line interface means and said data bus, and to said time slot assignment and control means, said transceiver com-prising:
receiver means for successively receiving first and second digital data words and the receive channel signalling bit associated with each in synchronization with a receive data clock provided by said switching system, said first digital data word being received from said data bus in response to said first receive enable signal, said second digital data word being received from said data bus in response to said second receive enable signal, and said receive channel signal-ling bits being received from said time slot assignment and control means;
modulation means for serially modulating said first and second digital data words and the respective receive channel signalling bits for transmission, in response to a sync signal provided by said switching system, to said transmit portion of said subscriber line via said subscriber line interface means;
sync detection means for detecting a modulated signal on said receive portion of said subscriber line via said subscriber line interface means; and for providing a valid sync signal in response to the detection thereof;
demodulation means for serially demodulating, in response to said valid sync signal, third and fourth digital data words and a transmit channel signalling bit associated with each, received on said receive portion of said subscriber line via said subscriber line interface means; and transmitter means for transmitting said third and fourth digital data words and the respective transmit channel signal-ling bits in synchronization with a transmit data clock provided by said switching system, said third digital data word being transmitted to said data bus in response to said first transmit enable signal, said second digital data word being transmitted to said data bus in response to said second transmit enable signal, and said transmit channel signalling bits being trans-mitted to said time slot assignment and control means.
6. A telecommunication subscriber line interface network comprising:
a digital subscriber set having substantially independent voice and data channels, said digital subscriber set comprising:
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
data channel means for receiving a digital information input data word provided to said digital subscriber set, and for transmitting from said digital subscriber set a received digital information output data word;
signalling means for selectively generating call control signals, including a transmit channel signalling bit, for each of said voice and data channels, and for providing an output signal in response to receiving a predetermined receive channel signalling bit for each of said voice and data channels;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and digital loop transceiver means coupled between said subscriber line interface means and said voice channel means, said data channel means and said signalling means, comprising:
sync detection means for detecting a modulated signal on said transmit portion of said subscriber line via said sub-scriber line interface means, providing a valid sync signal in response to the detection thereof, and providing first and second receive enable signals and first and second transmit enable signals in predetermined relationship to said detection;
demodulation means for serially demodulating, in response to said valid sync signal, said digital PCM voice output data word and said digital information output data word and a receive channel signalling bit associated with each, received from said transmit portion of said subscriber line via said subscriber line interface means;
transmitter means for transmitting said digital PCM voice output data word and said digital information output data word and the respective receive channel signalling bits in synchro-nization with a data clock developed by said transmitter means, said digital PCM voice output data word being transmitted to said voice channel means in response to said first transmit enable signal, said digital information output data word being transmitted to said data channel means in response to said second transmit enable signal, and said signalling bits being trans-mitted to said signalling means;
receiver means for successively receiving said digital PCM voice input data word and said digital information input data word and a transmit channel signalling bit associated with each, in synchronization with said data clock, said digital PCM
voice input data word being received from said voice channel means in response to said first receive enable signal, said digital information input data word being received from said data channel means in response to said second receive enable signal, and said transmit channel signalling bits being received from said signalling means; and modulation means for serially modulating said digital PCM voice input data word and said digital information input data word and the respective transmit channel signalling bits for tranmission in response to said valid sync signal to said receive portion of said subscriber line via said subscriber line interface means; and a telecommunication subscriber line interface circuit for coupling a ditital switching system having a digital data bus and a control bus via said duplex subscriber line to said digital subscriber set, said interface circuit comprising:
time slot assignment and control means coupled to said control bus and responsive to control signals received there-from and to first and second transmit channel signalling bits coupled thereto, for selectively providing first and second receive enable signals during respective first and second receive channel time slots, first and second transmit enable signals during respective first and second transmit channel time slots, and first and second receive channel signalling bits;
subscriber line interface means for coupling said inter face circuit to a transmit and a receive portion of said duplex subscriber line; and digital loop transceiver means coupled between said sub-scriber line interface means and said data bus, and to said time slot assignment and control means, said transceiver com-prising:
receiver means for successively receiving first and second digital data words and the receive channel signalling bit associated with each in synchronization with a receive data clock provided by said switching system, said first digital data word being received from said data bus in response to said first receive enable signal, said second digital data word being received from said data bus in response to said second receive enable signal, and said receive channel signal-ling bits being received from said time slot assignment and control means;
modulation means for serially modulating said first and second digital data words and the respective receive channel signalling bits for transmission, in response to a sync signal provided by said switching system, to said transmit portion of said subscriber line via said subscriber line interface means;
sync detection means for detecting a modulated signal on said receive portion of said subscriber line via said subscriber line interface means, and for providing a valid sync signal in response to the detection thereof;
demodulation means for serially demodulating in response to said valid sync signal, third and fourth digital data words and a transmit channel signalling bit associated with each, received on said receive portion of said subscriber line via said subscriber line interface means; and transmitter means for transmitting said third and fourth digital data words and the respective transmit channel signal-ling bits in synchronization with a transmit data clock provided by said switching system, said third digital data word being transmitted to said data bus in response to said first transmit enable signal, said second digital data word being transmitted to said data bus in response to said second transmit enable signal, and said transmit channel signalling bits being trans-mitted to said time slot assignment and control means.
a digital subscriber set having substantially independent voice and data channels, said digital subscriber set comprising:
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
data channel means for receiving a digital information input data word provided to said digital subscriber set, and for transmitting from said digital subscriber set a received digital information output data word;
signalling means for selectively generating call control signals, including a transmit channel signalling bit, for each of said voice and data channels, and for providing an output signal in response to receiving a predetermined receive channel signalling bit for each of said voice and data channels;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and digital loop transceiver means coupled between said subscriber line interface means and said voice channel means, said data channel means and said signalling means, comprising:
sync detection means for detecting a modulated signal on said transmit portion of said subscriber line via said sub-scriber line interface means, providing a valid sync signal in response to the detection thereof, and providing first and second receive enable signals and first and second transmit enable signals in predetermined relationship to said detection;
demodulation means for serially demodulating, in response to said valid sync signal, said digital PCM voice output data word and said digital information output data word and a receive channel signalling bit associated with each, received from said transmit portion of said subscriber line via said subscriber line interface means;
transmitter means for transmitting said digital PCM voice output data word and said digital information output data word and the respective receive channel signalling bits in synchro-nization with a data clock developed by said transmitter means, said digital PCM voice output data word being transmitted to said voice channel means in response to said first transmit enable signal, said digital information output data word being transmitted to said data channel means in response to said second transmit enable signal, and said signalling bits being trans-mitted to said signalling means;
receiver means for successively receiving said digital PCM voice input data word and said digital information input data word and a transmit channel signalling bit associated with each, in synchronization with said data clock, said digital PCM
voice input data word being received from said voice channel means in response to said first receive enable signal, said digital information input data word being received from said data channel means in response to said second receive enable signal, and said transmit channel signalling bits being received from said signalling means; and modulation means for serially modulating said digital PCM voice input data word and said digital information input data word and the respective transmit channel signalling bits for tranmission in response to said valid sync signal to said receive portion of said subscriber line via said subscriber line interface means; and a telecommunication subscriber line interface circuit for coupling a ditital switching system having a digital data bus and a control bus via said duplex subscriber line to said digital subscriber set, said interface circuit comprising:
time slot assignment and control means coupled to said control bus and responsive to control signals received there-from and to first and second transmit channel signalling bits coupled thereto, for selectively providing first and second receive enable signals during respective first and second receive channel time slots, first and second transmit enable signals during respective first and second transmit channel time slots, and first and second receive channel signalling bits;
subscriber line interface means for coupling said inter face circuit to a transmit and a receive portion of said duplex subscriber line; and digital loop transceiver means coupled between said sub-scriber line interface means and said data bus, and to said time slot assignment and control means, said transceiver com-prising:
receiver means for successively receiving first and second digital data words and the receive channel signalling bit associated with each in synchronization with a receive data clock provided by said switching system, said first digital data word being received from said data bus in response to said first receive enable signal, said second digital data word being received from said data bus in response to said second receive enable signal, and said receive channel signal-ling bits being received from said time slot assignment and control means;
modulation means for serially modulating said first and second digital data words and the respective receive channel signalling bits for transmission, in response to a sync signal provided by said switching system, to said transmit portion of said subscriber line via said subscriber line interface means;
sync detection means for detecting a modulated signal on said receive portion of said subscriber line via said subscriber line interface means, and for providing a valid sync signal in response to the detection thereof;
demodulation means for serially demodulating in response to said valid sync signal, third and fourth digital data words and a transmit channel signalling bit associated with each, received on said receive portion of said subscriber line via said subscriber line interface means; and transmitter means for transmitting said third and fourth digital data words and the respective transmit channel signal-ling bits in synchronization with a transmit data clock provided by said switching system, said third digital data word being transmitted to said data bus in response to said first transmit enable signal, said second digital data word being transmitted to said data bus in response to said second transmit enable signal, and said transmit channel signalling bits being trans-mitted to said time slot assignment and control means.
7. A digital loop transceiver circuit for providing duplex communication of digital data words on first and second channels and a signalling bit associated with said first channel, between a duplex subscriber line and a digital 1/0 port, the transceiver circuit comprising:
receiver means for successively receiving a first and a second of said digital data words and a first of said signal-ling bits in synchronization with a receive data clock, said first and second digital data words and said first signalling bit being received from said digital 1/0 port in response to a channel receive enable signal;
modulation means for serially modulating said first and second digital data words and said signalling bit for trans-mission via a first portion of said subscriber line;
sync detection means for detecting a modulated signal on a second portion of said subscriber line, and providing a valid sync signal in response to said detection;
demodulation means for serially demodulating, in response to said valid sync signal, a third and a fourth of said digital data words and a second of said signalling bits received via said second portion of said subscriber line; and transmitter means for transmitting said third and fourth digital data words and said second signalling bit in synchroni-zation with a transmit data clock, said third and fourth digital data words being transmitted to said digital 1/0 port in response to a first channel transmit enable signal.
receiver means for successively receiving a first and a second of said digital data words and a first of said signal-ling bits in synchronization with a receive data clock, said first and second digital data words and said first signalling bit being received from said digital 1/0 port in response to a channel receive enable signal;
modulation means for serially modulating said first and second digital data words and said signalling bit for trans-mission via a first portion of said subscriber line;
sync detection means for detecting a modulated signal on a second portion of said subscriber line, and providing a valid sync signal in response to said detection;
demodulation means for serially demodulating, in response to said valid sync signal, a third and a fourth of said digital data words and a second of said signalling bits received via said second portion of said subscriber line; and transmitter means for transmitting said third and fourth digital data words and said second signalling bit in synchroni-zation with a transmit data clock, said third and fourth digital data words being transmitted to said digital 1/0 port in response to a first channel transmit enable signal.
8. The digital loop transceiver circuit of claim 7 wherein said subscriber line comprises a pair of conductors, said first portion comprises said pair of conductors during a first period of time, and said second portion comprises said pair of conductors during a second period of time.
9. The digital loop transceiver circuit of claim 7 wherein said subscriber line comprises first and second pairs of conductors, said first portion comprises said first pair of conductors, and said second portion comprises said second pair of conductors.
10. A digital subscriber set having substantially indepen-dent voice and data channels, said digital subscriber set comprising:
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
data channel means for receiving a digital information input data word provided to said digital subscriber set, and for transmitting from said digital subscriber set a received digital information output data word;
signalling means for selectively generating a call control signal, including a transmit channel signalling bit, for said voice channel, and for providing an output signal in response to receiving a predetermined receive channel signalling bit for said voice channel;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and the digital loop transceiver means of claim 8 coupled between said subscriber line interface means and said voice channel means, said data channel means and said signalling means, wherein said digital PCM voice input data word, said digital information input data word, said digital PCM voice output data word, and said digital information output data word comprise said first, second, third and fourth digital data words, respectively, wherein said transmit channel signalling bit comprises said first signalling bit, and wherein said receive channel signalling bit comprises said second signal-ling bit.
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
data channel means for receiving a digital information input data word provided to said digital subscriber set, and for transmitting from said digital subscriber set a received digital information output data word;
signalling means for selectively generating a call control signal, including a transmit channel signalling bit, for said voice channel, and for providing an output signal in response to receiving a predetermined receive channel signalling bit for said voice channel;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and the digital loop transceiver means of claim 8 coupled between said subscriber line interface means and said voice channel means, said data channel means and said signalling means, wherein said digital PCM voice input data word, said digital information input data word, said digital PCM voice output data word, and said digital information output data word comprise said first, second, third and fourth digital data words, respectively, wherein said transmit channel signalling bit comprises said first signalling bit, and wherein said receive channel signalling bit comprises said second signal-ling bit.
11. A telecommunication subscriber line interface circuit fox coupling a digital switching system having a digital data bus and a control bus via a duplex subscriber line to a digital subscriber set having time multiplexed first and second digital data channels, the interface circuit comprising:
time slot assignment and control means coupled to said control bus and responsive to control signals received there-from and to a transmit channel signalling hit coupled thereto, for selectively providing a receive enable signal during a receive channel time slot, a transmit enable signal during a transmit channel time slot, and a receive channel signalling bit;
subscriber line interface means for coupling said inter-face circuit to a transmit and a receive portion of said duplex subscriber line; and the digital loop transceiver means of claim 8 coupled between said subscriber line interface means and said data bus, and to said time slot assignment and control means, wherein said transmit channel signalling bit comprises said first signal-ling bit, and wherein said receive channel signalling bit comprises said second signalling bit.
time slot assignment and control means coupled to said control bus and responsive to control signals received there-from and to a transmit channel signalling hit coupled thereto, for selectively providing a receive enable signal during a receive channel time slot, a transmit enable signal during a transmit channel time slot, and a receive channel signalling bit;
subscriber line interface means for coupling said inter-face circuit to a transmit and a receive portion of said duplex subscriber line; and the digital loop transceiver means of claim 8 coupled between said subscriber line interface means and said data bus, and to said time slot assignment and control means, wherein said transmit channel signalling bit comprises said first signal-ling bit, and wherein said receive channel signalling bit comprises said second signalling bit.
12. A digital loop transceiver circuit for providing duplex communication of digital data words on a channel and a signalling bit associated with said channel, between a duplex subscriber line and a digital 1/0 port, the transceiver circuit comprising:
receiver means for successively receiving a first of said digital data words and a first of said signalling bits in syn-chronization with a receive data clock, said first digital data word and said first signalling bit being received from said digital 1/0 port in response to a channel receive enable signal;
modulation means for serially modulating said first digital data word and said first signalling bit for transmission via a first portion of said subscriber line;
sync detection means for detecting a modulated signal on a second portion of said subscriber line, and providing a valid sync signal in response to said detection;
demodulation means for serially demodulating, in response to said valid sync signal, a second of said digital data words and a second of said signalling bits received via said second portion of said subscriber line; and transmitter means for transmitting said second digital data word and said second signalling bit in synchornization with a transmit data clock, said second digital data word being transmitted to said digital 1/0 port in response to a channel transmit enable signal.
receiver means for successively receiving a first of said digital data words and a first of said signalling bits in syn-chronization with a receive data clock, said first digital data word and said first signalling bit being received from said digital 1/0 port in response to a channel receive enable signal;
modulation means for serially modulating said first digital data word and said first signalling bit for transmission via a first portion of said subscriber line;
sync detection means for detecting a modulated signal on a second portion of said subscriber line, and providing a valid sync signal in response to said detection;
demodulation means for serially demodulating, in response to said valid sync signal, a second of said digital data words and a second of said signalling bits received via said second portion of said subscriber line; and transmitter means for transmitting said second digital data word and said second signalling bit in synchornization with a transmit data clock, said second digital data word being transmitted to said digital 1/0 port in response to a channel transmit enable signal.
13. The digital loop transceiver circuit of claim 12 where-in said subscriber line comprises a pair of conductors, said first portion comprises said pair of conductors during a first period of time, and said second portion comprises said pair of conductors during a second period of time.
14. The digital loop transceiver circuit of claim 12 wherein said subscriber line comprises first and second pair of conductors, said first portion comprises said first pair of conductors, and said second portion comprises said second pair of conductors.
15. A digital subscriber set comprising:
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
signalling means for selectively generating a call con-trol signal, including a transmit channel signalling bit, for said voice channel and for providing an output signal in response to receiving a predetermined receive channel signal-ling bit for said voice channel;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and the digital loop transceiver means of claim 13 coupled between said subscriber line interface means and said voice channel means, wherein said digital PCM voice input data word and said digital PCM voice output data word comprise said first and second digital data words; respectively, wherein said transmit channel signalling bit comprises said first signalling bit, and wherein said receive channel signalling bit comprises said second signalling bit.
voice channel means for periodically providing a digital PCM voice input data word representing a digitized voice input signal, and for receiving a digital PCM voice output data word for output as a voice output signal;
signalling means for selectively generating a call con-trol signal, including a transmit channel signalling bit, for said voice channel and for providing an output signal in response to receiving a predetermined receive channel signal-ling bit for said voice channel;
subscriber line interface means for coupling said digital subscriber set to transmit and receive portions of a duplex subscriber line; and the digital loop transceiver means of claim 13 coupled between said subscriber line interface means and said voice channel means, wherein said digital PCM voice input data word and said digital PCM voice output data word comprise said first and second digital data words; respectively, wherein said transmit channel signalling bit comprises said first signalling bit, and wherein said receive channel signalling bit comprises said second signalling bit.
16. A telecommunication subscriber line interface circuit for coupling a digital switching system having a digital data bus and a control bus via a duplex subscriber line to a digital subscriber set, the interface circuit comprising:
time slot assignment and control means coupled to said control bus and responsive to control signals received there-from and to a transmit channel signalling bit coupled thereto, for selectively providing a receive enable signal during a receive channel time slot, a transmit enable signal during a transmit channel time slot, and a receive channel signalling bit;
subscriber line interface means for coupling said inter-face circuit to a transmit and a receive portion of said duplex subscriber line; and the digital loop transceiver means of claim 13 coupled between said subscriber line interface means and said data bus, and to said time slot assignment and control means, wherein said transmit channel signalling bit comprises said first signalling bit, and wherein said receive channel signal-ling bit comprises said second signalling bit.
time slot assignment and control means coupled to said control bus and responsive to control signals received there-from and to a transmit channel signalling bit coupled thereto, for selectively providing a receive enable signal during a receive channel time slot, a transmit enable signal during a transmit channel time slot, and a receive channel signalling bit;
subscriber line interface means for coupling said inter-face circuit to a transmit and a receive portion of said duplex subscriber line; and the digital loop transceiver means of claim 13 coupled between said subscriber line interface means and said data bus, and to said time slot assignment and control means, wherein said transmit channel signalling bit comprises said first signalling bit, and wherein said receive channel signal-ling bit comprises said second signalling bit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US334,412 | 1981-12-24 | ||
| US06/334,412 US4432089A (en) | 1981-12-24 | 1981-12-24 | Digital loop transceiver for interfacing a digital PABX to a digital subscriber set via a subscriber line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1187969A true CA1187969A (en) | 1985-05-28 |
Family
ID=23307090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000414134A Expired CA1187969A (en) | 1981-12-24 | 1982-10-25 | Digital loop transceiver for interfacing a digital pabx to a digital subscriber set via a subscriber line |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4432089A (en) |
| EP (1) | EP0097166B1 (en) |
| JP (1) | JPS59500037A (en) |
| CA (1) | CA1187969A (en) |
| DE (1) | DE3278065D1 (en) |
| HK (1) | HK65290A (en) |
| WO (1) | WO1983002379A1 (en) |
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| US5402413A (en) * | 1991-04-08 | 1995-03-28 | Omnipoint Corporation | Three-cell wireless communication system |
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Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE332201B (en) * | 1969-07-02 | 1971-02-01 | Ericsson Telefon Ab L M | |
| US3924077A (en) * | 1973-07-05 | 1975-12-02 | Thomas R Blakeslee | Pulse code modulation time division multiplex telephone system |
| GB1479009A (en) * | 1974-07-12 | 1977-07-06 | Sarma B | Telecommunication switching system |
| DE2643687C2 (en) * | 1976-09-28 | 1983-09-29 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for the transmission of digital signals between subscriber stations of a time division multiplex telecommunications network, in particular PCM time division multiplex telecommunications network |
| DE2819119C3 (en) * | 1978-04-29 | 1980-10-30 | Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt | Circuit arrangement for time-division multiplex digitally switching telecommunication systems, in particular telephone switching systems |
| CA1123102A (en) * | 1979-07-27 | 1982-05-04 | Harold H. Harris | Line interface unit for voice and wide band signal coupling |
| DE3010702C2 (en) * | 1980-03-20 | 1982-11-04 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Digital messaging system |
| US4450556A (en) * | 1980-10-17 | 1984-05-22 | Northern Telecom Limited | Digital signal subscriber loop and interface circuit |
-
1981
- 1981-12-24 US US06/334,412 patent/US4432089A/en not_active Expired - Lifetime
-
1982
- 1982-10-04 EP EP82903416A patent/EP0097166B1/en not_active Expired
- 1982-10-04 WO PCT/US1982/001435 patent/WO1983002379A1/en active IP Right Grant
- 1982-10-04 DE DE8282903416T patent/DE3278065D1/en not_active Expired
- 1982-10-04 JP JP82503422A patent/JPS59500037A/en active Pending
- 1982-10-25 CA CA000414134A patent/CA1187969A/en not_active Expired
-
1990
- 1990-08-23 HK HK652/90A patent/HK65290A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0097166A1 (en) | 1984-01-04 |
| HK65290A (en) | 1990-08-31 |
| EP0097166B1 (en) | 1988-01-27 |
| US4432089A (en) | 1984-02-14 |
| EP0097166A4 (en) | 1984-05-29 |
| JPS59500037A (en) | 1984-01-05 |
| DE3278065D1 (en) | 1988-03-03 |
| WO1983002379A1 (en) | 1983-07-07 |
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