CA2658561C - Low output skew double data rate serial encoder - Google Patents
Low output skew double data rate serial encoder Download PDFInfo
- Publication number
- CA2658561C CA2658561C CA2658561A CA2658561A CA2658561C CA 2658561 C CA2658561 C CA 2658561C CA 2658561 A CA2658561 A CA 2658561A CA 2658561 A CA2658561 A CA 2658561A CA 2658561 C CA2658561 C CA 2658561C
- Authority
- CA
- Canada
- Prior art keywords
- output
- multiplexer
- serial
- encoder
- serial encoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
Abstract
A Double Data Rate (DDR) serial encoder is provided. In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced. In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output, thereby resulting in a reduced output skew and increased link rate.
Description
LOW OUTPUT SKEW DOUBLE DATA RATE SERIAL ENCODER
BACKGROUND
Field [0003] The present invention relates generally to a serial encoder for high data rate serial communication links. More particularly, the invention relates to a double data rate serial encoder for Mobile Display Interface (MDDI) links.
Background [0004] In the field of interconnect technologies, demand for ever increasing data rates, especially as related to video presentations, continues to grow.
[0005] The Mobile Display Digital Interface (MDDI) is a cost-effective, low power consumption, transfer mechanism that enables very-high-speed data transfer over a short-range communication link between a host and a client.
MDDI
requires a minimum of just four wires plus power for bi-directional data transfer that delivers a maximum bandwidth of up to 3.2 Gbits per second.
BACKGROUND
Field [0003] The present invention relates generally to a serial encoder for high data rate serial communication links. More particularly, the invention relates to a double data rate serial encoder for Mobile Display Interface (MDDI) links.
Background [0004] In the field of interconnect technologies, demand for ever increasing data rates, especially as related to video presentations, continues to grow.
[0005] The Mobile Display Digital Interface (MDDI) is a cost-effective, low power consumption, transfer mechanism that enables very-high-speed data transfer over a short-range communication link between a host and a client.
MDDI
requires a minimum of just four wires plus power for bi-directional data transfer that delivers a maximum bandwidth of up to 3.2 Gbits per second.
2 [00061 In one application, MDDI increases reliability and decreases power consumption in clamshell phones by significantly reducing the number of wires that run across a handset's hinge to interconnect the digital baseband controller with an LCD display and/or a camera. This reduction of wires also allows handset manufacturers to lower development costs by simplifying clamshell or sliding handset designs.
[00071 MDDI is a serial transfer protocol, and, as such, data received in parallel for transmission over an MDDI link needs to be serialized. U.S. Patent Application No.
11/285,397, entitled "Double Data Rate Serial Encoder", filed November 23, describes an MDDI Double Data Rate (DDR) serial encoder having a glitchless output. The glitchless output serial encoder benefits from a glitchless multiplexer, designed with a priori knowledge of a Gray code input select sequence. This a priori knowledge of the input select sequence allows for a reduction in the size of the multiplexer and, subsequently, of that of the DDR serial encoder.
[00081 However, improvements can be made in several aspects to the DDR
serial encoder design described in U.S. Application No. 11/285,397. In one aspect, it is
[00071 MDDI is a serial transfer protocol, and, as such, data received in parallel for transmission over an MDDI link needs to be serialized. U.S. Patent Application No.
11/285,397, entitled "Double Data Rate Serial Encoder", filed November 23, describes an MDDI Double Data Rate (DDR) serial encoder having a glitchless output. The glitchless output serial encoder benefits from a glitchless multiplexer, designed with a priori knowledge of a Gray code input select sequence. This a priori knowledge of the input select sequence allows for a reduction in the size of the multiplexer and, subsequently, of that of the DDR serial encoder.
[00081 However, improvements can be made in several aspects to the DDR
serial encoder design described in U.S. Application No. 11/285,397. In one aspect, it is
3 noted that the glitchless multiplexer used in the DDR serial encoder described in U.S.
Application No. 11/285,397 remains larger in size than a non-glitchless multiplexer. In another aspect, the number of logic layers between the final register stage and the encoder output, a factor that contributes to larger output skew and lower link rate, can be significantly reduced.
[0009] What is needed therefore is an MDDI DDR serial encoder having reduced size, complexity, and output skew. What is also needed is that the MDDI DDR serial encoder has a glitchless output.
BRIEF SUMMARY OF THE INVENTION
[0010] A Double Data Rate (DDR) serial encoder is provided herein.
[0011] In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced.
[0012] In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output and a reduced number of paths from the final register stage to the encoder output, thereby resulting in reduced output skew and increased link rate. The reduced number of paths from the final register stage to the encoder output also simplifies output skew analysis.
[0012a] According to one aspect of the present invention, there is provided a serial encoder comprising: means for storing a plurality of data input bits; means for storing a plurality of select input bits; means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage, wherein the output of said serial outputting means is coupled to a data input of the clock-driven register stage, and wherein said register stage is ' 74769-2275
Application No. 11/285,397 remains larger in size than a non-glitchless multiplexer. In another aspect, the number of logic layers between the final register stage and the encoder output, a factor that contributes to larger output skew and lower link rate, can be significantly reduced.
[0009] What is needed therefore is an MDDI DDR serial encoder having reduced size, complexity, and output skew. What is also needed is that the MDDI DDR serial encoder has a glitchless output.
BRIEF SUMMARY OF THE INVENTION
[0010] A Double Data Rate (DDR) serial encoder is provided herein.
[0011] In one aspect, the DDR serial encoder includes a non-glitchless multiplexer and digital logic for ensuring a glitch-free encoder output. By using a non-glitchless multiplexer, the size and complexity of the encoder is significantly reduced.
[0012] In another aspect, the DDR serial encoder has a single layer of logic between the final register stage and the encoder output and a reduced number of paths from the final register stage to the encoder output, thereby resulting in reduced output skew and increased link rate. The reduced number of paths from the final register stage to the encoder output also simplifies output skew analysis.
[0012a] According to one aspect of the present invention, there is provided a serial encoder comprising: means for storing a plurality of data input bits; means for storing a plurality of select input bits; means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage, wherein the output of said serial outputting means is coupled to a data input of the clock-driven register stage, and wherein said register stage is ' 74769-2275
4 separated by a single logic layer from the serial encoder output, thereby resulting in a low output skew of the encoder.
[0012b] According to another aspect of the present invention, there is provided a serial encoder, comprising: means for storing a plurality of data input bits; means for storing a plurality of select input bits; means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage which outputs two signals and means for selecting one of the two signals as the serial encoder output, and wherein the serial encoder output is solely determined by two signals from said register stage, thereby resulting in a low output skew of the encoder, wherein the output of said serial outputting means is coupled to a data input of the clock-driven register stage.
[0012c] According to still another aspect of the present invention, there is provided a method of serial encoding, comprising: providing a first multiplexer having a plurality of data inputs, a plurality of select inputs, and an output; providing a plurality of data input flip-flops coupled to the data inputs of the first multiplexer; providing a plurality of select input flip-flops coupled to the select inputs of the first multiplexer; and providing a synchronizing circuit coupled to the output of the first multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage which outputs two signals and a second multiplexer for selecting one of the two signals as the serial encoder output, thereby resulting in a low output skew of the encoder, wherein the output of said first multiplexer is coupled to a data input of the final data register stage, and employing the synchronizing circuit to substantially eliminate output glitches from the output of the first multiplexer.
[0013] Further embodiments, features, and advantages, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
4a BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of embodiments of the invention and to enable a person skilled in the pertinent art to make and use the embodiments of the invention.
[0015] FIG. 1 is a block diagram that illustrates an example environment using a Mobile Display Digital Interface (MDDI) interface.
[0016] FIG. 2 is a block diagram that illustrates an MDDI link interconnection according to an embodiment of the example of FIG. 1.
[0017] FIG. 3 is a circuit diagram that illustrates an MDDI serial encoder.
[0018] FIGs. 4A-B illustrate examples of signal skew.
[0019] FIG. 5 is a block diagram that illustrates an MDDI serial encoder according to an embodiment of the present invention.
[0020] FIG. 6 is a circuit diagram that illustrates an MDDI serial encoder according to another embodiment of the present invention.
[0021] FIG. 7 is an example timing diagram relating signals of the MDDI serial encoder of FIG. 6.
[0022] FIG. 8 is a circuit diagram that illustrates an MDDI serial encoder according to a further embodiment of the present invention.
[0023] FIG. 9 is an example timing diagram relating signals of the MDDI
serial encoder of FIG. 8.
[0024] The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.
DETAILED DESCRIPTION
100251 This specification discloses one or more embodiments that incorporate the features of this invention. The disclosed embodiment(s) merely exemplify the invention. The scope of the invention is not limited to the disclosed embodiment(s).
The invention is defined by the claims appended hereto.
100261 The embodiment(s) described, and references in the specification to "one embodiment", "an embodiment", "an example embodiment", etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
100271 Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact result from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc.
Mobile Display Digital Interface (MDDI) [0028] The Mobile Display Digital Interface (MDDI) is a cost-effective, low power consumption, transfer mechanism that enables very-high-speed serial data transfer over a short-range communication link between a host and a client.
[0029] In the following, examples of MDDI will be presented with respect to a camera module contained in an upper clamshell of a mobile phone. However, it would be apparent to persons skilled in the relevant art(s) that any module having functionally equivalent features to the camera module could be readily substituted and used in various embodiments of this invention.
[0030] Further, according to embodiments of the invention, an MDDI host may comprise one of several types of devices that can benefit from using the present invention. For example, the host could be a portable computer in the form of a handheld, laptop, or similar mobile computing device. It could also be a Personal Data Assistant (PDA), a paging device, or one of many wireless telephones or modems. Alternatively, the host could be a portable entertainment or presentation device such as a portable DVD or CD player, or a game playing device.
Furthermore, the host can reside as a host device or control element in a variety of other widely used or planned commercial products for which a high speed communication link with a client is desired. For example, a host could be used to transfer data at high rates from a video recording device to a storage based client for improved response, or to a high resolution larger screen for presentations. An appliance such as a refrigerator that incorporates an onboard inventory or computing system and/or Bluetooth connections to other household devices, can have improved display capabilities when operating in an internet or Bluetooth connected mode, or have reduced wiring needs for in-the-door displays (a client) and keypads or scanners (client) while the electronic computer or control systems (host) reside elsewhere in the cabinet. In general, those skilled in the art will appreciate the wide variety of modern electronic devices and appliances that may benefit from the use of this interface, as well as the ability to retrofit older devices with higher data rate transport of information utilizing limited numbers of conductors available in either newly added or existing connectors or cables.
At the same time, an MDDI client may comprise a variety of devices useful for presenting information to an end user, or presenting information from a user to the host.
For example, a micro-display incorporated in goggles or glasses, a projection device built into a hat or helmet, a small screen or even holographic element built into a vehicle, such as in a window or windshield, or various speaker, headphone, or sound systems for presenting high quality sound or music. Other presentation devices include projectors or projection devices used to present information for meetings, or for movies and television images. Other examples include the use of touch pads or sensitive devices, voice recognition input devices, security scanners, and so forth that may be called upon to transfer a significant amount of information from a device or system user with little actual "input" other than touch or sound from the user. In addition, docking stations for computers and car kits or desk-top kits and holders for wireless telephones may act as interface devices to end users or to other devices and equipment, and employ either clients (output or input devices such as mice) or hosts to assist in the transfer of data, especially where high speed networks are involved. However, those skilled in the art will readily recognize that the present invention is not limited to these devices, there being many other devices on the market, and proposed for use, that are intended to provide end users with high quality images and sound, either in terms of storage and transport or in terms of presentation at playback. The present invention is useful in increasing the data throughput between various elements or devices to accommodate the high data rates needed for realizing the desired user experience.
[0031] FIG. 1 is a block diagram that illustrates an example environment using an MDDI interface. In the example of FIG. 1, MDDI is used to interconnect modules across the hinge of a clamshell phone 100. It must be noted here that while certain embodiments of the present invention will be described in the context of specific examples, such as MDDI interconnections in a clamshell phone, this is done for illustration purposes only and should not be used to limit the present invention to such embodiments. As will be understood by a person skilled in the relevant art(s) based on the teachings herein, embodiments of the present invention may be used in other devices including any that may benefit from having MDDI
interconnections.
[0032] Referring to FIG. 1, a lower clamshell section 102 of clamshell phone 100 includes a Mobile Station Modem (MSM) baseband chip 104. MSM 104 is a digital baseband controller. An upper clamshell section 114 of clamshell phone 100 includes a Liquid Crystal Display (LCD) module 116 and a camera module 118.
[0033] Still referring to FIG. 1, an MDDI link 110 connects camera module 118 to MSM 104. Typically, an MDDI link controller is integrated into each of camera module 118 and MSM 104. In the example of FIG. 1, an MDDI Host 122 is integrated into camera module 112, while an MDDI Client 106 resides on the MSM
side of the MDDI link 110. Typically, the MDDI host is the master controller of the MDDI link. In the example of FIG. 1, pixel data from camera module 118 are received and formatted into MDDI packets by MDDI Host 122 before being transmitted onto MDDI link 110. MDDI client 106 receives the MDDI packets and re-converts them into pixel data of the same format as generated by camera module 118. The pixel data are then sent to an appropriate block in MSM 104 for processing.
[0034] Still referring to FIG. 1, an MDDI link 112 connects LCD module 116 to MSM 104. In the example of FIG. 1, MDDI link 112 interconnects an MDDI Host 108, integrated into MSM 104, and an MDDI Client 120 integrated into LCD
module 116. In the example of FIG. 1, display data generated by a graphics controller of MSM 104 are received and formatted into MDDI packets by MDDI Host 108 before being transmitted onto MDDI link 112. MDDI client 120 receives the MDDI
packets and re-converts them into display data for use by LCD module 116.
100351 FIG. 2 is a block diagram that illustrates MDDI link interconnection 110 according to the example of FIG. 1. As described above, one of the functions of MDDI link 110 is to transfer pixel data from camera module 118 to MSM 104.
Accordingly, in the embodiment of FIG. 2, a frame interface 206 connects camera module 118 to MDDI Host 122. The frame interface 206 serves to transfer pixel data from camera module 118 to MDDI Host 122.
100361 Typically, camera module 118 receives pixel data from a camera through a parallel interface, stores the pixel data, and then transfers it to MDDI Host 122 when the host is ready. MDDI Host 122 encapsulates the received pixel data into MDDI
packets. However, in order for MDDI Host 122 to be able to transmit the pixel data onto MDDI link 110, a serialization of the MDDI packets is necessary.
100371 In the embodiment of FIG. 2, a serializer module 202, integrated within MDDI Host 122, serves to serially shift out the MDDI packets onto MDDI link 110.
At the MSM end of MDDI link 110, a de-serializer module 204, integrated within MDDI client 106, re-constructs the MDDI packets from the serial data received over MDDI link 110. MDDI client 106 then removes the MDDI encapsulation and transfers the parallel pixel data through a frame interface 208 to an appropriate block of MSM 104.
MDDI Serial Encoder 100381 FIG. 3 is a circuit diagram that illustrates an MDDI serial encoder 300.
MDDI serial encoder 300 is described in more detail in U.S. Application No.
11/285,397, entitled "Double Data Rate Serial Encoder", filed November 23, 2005.
Serial encoder 300 includes a final data register stage, illustrated using flip-flops 320 and 322, a select input register stage, illustrated using flip-flops 314, 316, and 318, and a glitchless multiplexer circuitry 324.
[0039] The final data register stage flip-flops 320 and 322 receive data input signals 308 and 310, respectively. In one embodiment, data input signals 308 and 310 are each 4 bits. Accordingly, flip-flops 320 and 322 are each 4-bit flip-flops. In other embodiments, flip-flops 320 and 322 may be replaced with four 2-bit flip-flops or eight 1-bit flip-flops. As illustrated in FIG. 3, flip-flops 320 and 322 are D
flip-flops, but other types of flip-flops or registers may also be used as understood by a person skilled in the art based on the teachings herein. Flip-flops 320 and 322 are controlled by a clock signal 312 and update their outputs at every rising edge of clock signal 312.
[0040] The select input register stage flip-flops 314, 316, and 318 receive select input signals sel(2) 302, sel(1) 304, and sel(0) 306, respectively. Select input signals 302, 304, and 306 are typically provided by a counter and are used to select the input of multiplexer circuitry 324. In one embodiment, select signals 302, 304, and 306 are generated according to a Gray code sequence, which is known a priori by multiplexer circuitry 324, thereby allowing a glitchless multiplexer output.
Flip-flops 314, 316, and 318 are D flip-flops, but other types of flip-flops may also be used as understood by a person skilled in the art based on the teachings herein.
Flip-flops 314, 316, and 318 are also controlled by clock signal 312, with flip-flop 318 updating its output at rising edges of clock signal 312 and flip-flops 314 and 316 updating their outputs at falling edges of clock signal 312.
[0041] Multiplexer circuitry 324 receives data input signals from the final data register stage and input select signals from the select input register stage, and generates the output 334 of serial encoder 300. Multiplexer circuitry 324 generates a glitchless encoder output using a priori knowledge of the Gray code input select sequence. Multiplexer circuitry 324 includes four layers of logic 326, 328, 330, and 332 that separate the final data register stage (flip-flops 320 and 322) and the select input register stage (flip-flops 318, 320, and 322) from the encoder output 334. Logic layer 326 includes inverter circuitry on certain paths from the select input register stage to the encoder output. Logic layer 326 is coupled via an interconnect to logic layer 328, which includes a plurality of AND gates. In turn, logic layer 328 is coupled via an interconnect to logic layer 330. Logic layer 330 includes a plurality of OR gates, which provide the inputs of logic layer 332. Logic layer 332 includes an OR gate that provides the output 334 of the serial encoder.
[0042] It is noted that the four logic layers 326, 328, 330, and 332 of multiplexer circuitry 324 are based on combinatorial logic and are not driven by clock signals.
Accordingly, signal propagation delays on different paths from the final data register stage and/or the select input register stage to the encoder output may be different.
Further, signal propagation delays could vary according to temperature and/or process variations in the encoder circuitry, making them difficult to monitor and/or to compensate for.
[0043] Typically, having different signal propagation delays on paths to the encoder output results in what is known as "output skew", with the actual encoder output being skewed or distorted relative to a desired nominal output. Output skew may also result from the skewing of a single signal that contributes to the encoder output.
100441 FIGs. 4A-B illustrate examples of signal skew. FIG. 4A
illustrates skew in an example signal 400, whereby falling and/or rising edges may occur earlier or later than when they should ideally occur. FIG. 4B illustrates skew between two signals Output 1 and Output 2. Output 1 and Output 2 result from synchronized input signals 402 and 402 propagating through paths 406 and 408 respectively of exemplary circuit 414, with paths 406 and 408 having different signal propagation delays. The skew between signals Output 1 and Output 2, illustrated as "tsk"
in FIG.
4B, represents the time difference magnitude between signals Output 1 and Output 2, which ideally would occur simultaneously. Note that the skew between signals Output 1 and Output 2 could result in an output skew at output 412 of exemplary circuit 414.
[0045] In certain cases, output skew may cause a reduction in the maximum MDDI
link rate. It is evident therefore that output skew should be minimized.
Low Output Skew MDDI Serial Encoder [0046] According to the present invention, output skew is reduced by minimizing the effects of factors that contribute thereto. In one aspect, output skew is affected by the individual skew of each signal (from the final data register stage and/or the select input register stage) that contributes to the encoder output. In another aspect, output skew is proportional to the magnitudes of these individual signal skews, which, in turn, are proportional to the lengths of their respective signal paths (a function of the number of successive logic layers to reach the encoder output).
[0047] As such, output skew can be reduced by minimizing: (1) the number of signals (from the final data register stage and/or select input register stage) that contribute to the encoder output, and (2) the number of logic layers from the final data register stage and/or the select input register stage to the encoder output.
[0048] FIG. 5 is a block diagram that illustrates an MDDI serial encoder according to an embodiment of the present invention. Serial encoder 500 includes a non-glitchless multiplexer 506 and a synchronizing circuit 510.
[0049] Non-glitchless multiplexer 506 receives data input signal 504 and input select signals 502 and generates output signal 508. In an embodiment, data input signal 504 includes an 8-bit signal. In other embodiments, data input signal 504 includes two 4-bit signals, four 2-bit signals, or eight 1-bit signals. Input select signals 502 control multiplexer 506 to couple one of the received data input signals to the output of the multiplexer. Typically, the number, N, of input select signals 502 is such that 2N equals the number of data bits in signal 504. In FIG. 5, the number of input select signals 502 is 3, making multiplexer 506 an 8:1 multiplexer.
[0050] Since the output 508 of multiplexer 506 may be non-glitchless, serial encoder 500 can be significantly simplified. In one aspect, data bits in input signal 504 are allowed to switch at any time and not only when they are not being selected for output, as in a glitchless multiplexer. In another aspect, the input selection sequence carried by input select signals 502 no longer need to adhere to a Gray code sequence.
[0051] Accordingly, to generate a glitchless encoder output, a synchronizing circuit 510 is used to ensure that any glitches in output 508 are removed at encoder output 512. In one embodiment, synchronizing circuit 510 includes a clock-driven final data register stage that enables signals contributing to the encoder output to have minimal skew relative to each other. In addition, the final data register stage is a very small number of logic layers away from the encoder output, further reducing output skew.
[0052] FIG. 6 is a circuit diagram that illustrates an MDDI serial encoder 600 according to another embodiment of the present invention.
[0053] Serial encoder 600 includes a data register stage, illustrated using flip-flop 620, a select input register stage, illustrated using flip-flops 612, 614, and 616, a multiplexer 622, and a synchronizing circuit 626.
[0054] The data register stage flip-flop 620 receives data input signal 610. In one embodiment, data input signal 610 includes an 8-bit signal. Accordingly, flip-flop 620 is an 8-bit flip-flop. In other embodiments, flip-flop 620 may be replaced with two 4-bit flip-flops, four 2-bit flip-flops, or eight 1-bit flip-flops. As illustrated in FIG. 6, flip-flop 620 is a D flip-flop, but other types of flip-flops or registers may also be used as understood by a person skilled in the art based on the teachings herein.
[0055] The select input register stage flip-flops 612, 614, and 616 receive select input signals sel(2) 602, sel(1) 604, and sel(0) 606, respectively. Select input signals 602, 604, and 606 are typically provided by a counter and are used to select the input of multiplexer 622. Select signals 602, 604, and 606 need not adhere to any type of input selection sequence, such as a Gray code sequence, for example. Flip-flops 612, 614, and 616 are D flip-flops, but other types of flip-flops may also be used as understood by a person skilled in the art based on the teachings herein.
[0056] Multiplexer 622 receives data input signals from the data register stage and input select signals from the select input register stage, and generates output signal 624. In one embodiment, multiplexer 622 is an 8:1 multiplexer.
[0057] Multiplexer 622 is a non-glitchless multiplexer. In other words, glitches may occur in output 624 of multiplexer 622. Accordingly, output 624 of multiplexer is provided to a synchronizing circuit 626 to ensure that any glitches in output 624 are removed at encoder output 642.
[0058] Synchronizing circuit 626 includes a first XOR stage, illustrated using XOR
gates 628 and 630, a final data register stage, illustrated using flip-flops 632, 634, 636, and 638, and a final XOR stage, illustrated using XOR gate 640, to generate encoder output 642.
[0059] The first XOR stage gates 628 and 630 receive output signal 624 and feedback signals from flip-flops 636 and 634, respectively. The outputs of XOR gates 628 and 630 are respectively received by flip-flops 632, 634 and 636, 638. Flip-flops 632, 634, 636, and 638 are controlled by a clock signal clk, with flip-flops 632 and 634 updating outputs at rising edges of the clock signal and flip-flops 636 and updating outputs at falling edges of the clock signal.
[0060] Flip-flops 634 and 636 are feedback flip-flops of the final data register stage having their outputs cross-coupled to XOR gates 628 and 630 of the first XOR
stage.
In other embodiments, the feedback signals to XOR gates 628 and 630 are provided from the outputs of flip-flops 638 and 632 respectively, with flip-flops 634 and 636 eliminated from the final data register stage. A more stable design, however, is achieved by using flip-flops 634 and 636 to provide the feedback signals to the first XOR stage. This reduces any additional routing of the outputs of flip-flops 632 and 638, which then need to only be input into the final XOR stage of synchronizing circuit 626.
[0061] The final XOR stage of synchronizing circuit 626 includes a single XOR gate 640, which receives the outputs of flip-flops 632 and 638 and outputs encoder output 642. Encoder output 642 is a glitchless output with low output skew.
[0062] It is noted that in serial encoder 600, a single layer of logic separates the final data register stage from the encoder output. Accordingly, the individual skew of signals contributing to the encoder output remains very low. Further, it is noted that only two signals from the final data register stage (outputs of flip-flops 632 and 638) contribute to encoder output 642, further reducing output skew. The reduced number of paths from the final register stage to the encoder output also simplifies output skew analysis.
100631 FIG. 8 is a circuit diagram that illustrates an MDDI serial encoder 800 according to a further embodiment of the present invention. MDDI serial encoder 800 is similar in several respects to MDDI serial encoder 600 of FIG. 6, but employs a different synchronizing circuit implementation 812. It is noted that, in practice, the synchronizing circuit is equivalent to a dual edge flip-flop, and accordingly, any implementation of a dual edge flip-flop or functionally equivalent circuitry may be used for the synchronizing circuit according to embodiments of the present invention.
100641 In FIG. 8, synchronizing circuit 812 includes a final data register stage, illustrated using flip flops 804 and 806, and a multiplexer 808. Flip flops 804 and 806 receive output signal 624 of multiplexer 622 and are controlled by clock signal 802, with flip flop 804 updating its output at rising edges of clock signal 802 and flip flop 806 updating its output at falling edges of clock signal 802. The outputs of flip flops 804 and 806 subsequently form inputs to multiplexer 808. Multiplexer 808 is also controlled by clock signal 802, with the output of flip flop 804 being output from multiplexer 808 when the clock signal 802 is high and the output of flip flop being output from multiplexer 808 when the clock signal 802 is low, to generate the encoder output 810. It is noted that, in embodiment 800, the encoder output has a race condition on clock signal 802. This race condition is a result of a rising or falling edge in clock signal 802 causing the currently selected input to multiplexer 808 to change. The encoder output 810 is glitchless only if a rising or falling edge of clock signal 802 has selected the other input of the multiplexer 808 as the encoder output 810 before the current input changes. As an example, when clock signal is low, the output of flip flop 806 is being output from multiplexer 808 as encoder output 810. At a rising edge of the clock signal 802, the output of flip flop 806 will update to a new state while at the same time the output of flip flop 804 is selected as the output of multiplexer 808 as encoder output 810. To avoid glitches on encoder output 810, the delay from clock signal 802 through multiplexer 808 to the encoder output 810 must be less than the delay from clock signal 802 through flip flops 804 or 806 to multiplexer 808. As long as this timing condition is met, encoder output 810 is a glitchless output with low output skew.
[0065] It is also noted that in serial encoder 800, a single layer of logic separates the final data register stage from the encoder output with only two signals from the final data register stage contributing to encoder output 810, thereby resulting in a reduced output skew and simplified output skew analysis.
Example Timing Diagrams [0066] FIG. 7 is an example timing diagram relating signals of MDDI
serial encoder 600 of FIG. 6. In this example diagram, the select inputs transitions, illustrated as signal sel[2:0] in FIG. 7, are in accordance with a Gray code sequence as typically required for MDDI encoders with glitchless multiplexer. Accordingly, multiplexer 622 of FIG. 6 operates identically to a glitchless multiplexer, but without the glitch free output requirement. Note that the select inputs sequence in FIG. 7 is an exemplary one and that other select inputs sequences may also be used.
[0067] Signal din[7:0] in FIG. 7 corresponds to data input signal 610 in FIG. 6. An exemplary sequence of signal din[7:0] is provided in FIG. 7.
[0068] Signal din_reg[7:0] corresponds to signal din_reg[7:0] illustrated in FIG. 6, and can be generated from signal din[7:0] according to signal data_en in FIG.
7. An exemplary sequence of signal din_reg[7:0] is provided in FIG. 7.
[0069] Signal desired_data_out corresponds to signal 624 in FIG. 6.
[0070] Signals out_rise and out fall correspond to the outputs of flip-flops 632 and 638, respectively. Note that out_rise = (desired_data_out XOR out fall) and that out_fall = (desired_data_out XOR out_rise). Also note that signal dout =
out_rise XOR out_fall. Accordingly, either of the two final output registers can drive the desired_data_out value to dout by holding or inverting its output. Signal dout is equivalent to signal desired_data_out but is delayed by 1/2 clock cycle.
[0071] FIG. 9 is an example timing diagram relating signals of MDDI serial encoder 800 of FIG. 8. Similar to the example timing diagram of FIG. 7, the select inputs transitions, illustrated as sel[2:0] in FIG. 9, are in accordance with a Gray code sequence as typically required for MDDI encoders with glitchless multiplexer.
Note, however, that the select inputs sequence illustrated in FIG. 9 is only exemplary and that other select inputs sequences may also be used.
[0072] Signal (11147:0] in FIG. 9 corresponds to data input signal 610 in FIG. 8. An exemplary sequence of signal din[7:01 is provided in FIG. 9.
[0073] Signal din_reg[7:0] corresponds to the output of flip-flop 620 in FIG. 8. An exemplary sequence of signal din_reg[7:0] is provided in FIG. 9.
[0074] Signal desired_data_out corresponds to signal 624 in FIG. 8.
[0075] Signals pos_reg and neg_reg correspond to the outputs of flip-flops 804 and 806, respectively, in FIG. 8.
[0076] Signal dout corresponds to encoder output dout 810 in FIG. 8. Note that dout is equivalent to desired_data_out signal, but is delayed by 1 clock cycle, with 1/2 clock cycle delay due to flip-flops 804 and 806 and lh clock cycle delay due to multiplexer 808.
Conclusion =
[0077] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the scope of the claims. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims.
[0012b] According to another aspect of the present invention, there is provided a serial encoder, comprising: means for storing a plurality of data input bits; means for storing a plurality of select input bits; means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage which outputs two signals and means for selecting one of the two signals as the serial encoder output, and wherein the serial encoder output is solely determined by two signals from said register stage, thereby resulting in a low output skew of the encoder, wherein the output of said serial outputting means is coupled to a data input of the clock-driven register stage.
[0012c] According to still another aspect of the present invention, there is provided a method of serial encoding, comprising: providing a first multiplexer having a plurality of data inputs, a plurality of select inputs, and an output; providing a plurality of data input flip-flops coupled to the data inputs of the first multiplexer; providing a plurality of select input flip-flops coupled to the select inputs of the first multiplexer; and providing a synchronizing circuit coupled to the output of the first multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage which outputs two signals and a second multiplexer for selecting one of the two signals as the serial encoder output, thereby resulting in a low output skew of the encoder, wherein the output of said first multiplexer is coupled to a data input of the final data register stage, and employing the synchronizing circuit to substantially eliminate output glitches from the output of the first multiplexer.
[0013] Further embodiments, features, and advantages, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
4a BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of embodiments of the invention and to enable a person skilled in the pertinent art to make and use the embodiments of the invention.
[0015] FIG. 1 is a block diagram that illustrates an example environment using a Mobile Display Digital Interface (MDDI) interface.
[0016] FIG. 2 is a block diagram that illustrates an MDDI link interconnection according to an embodiment of the example of FIG. 1.
[0017] FIG. 3 is a circuit diagram that illustrates an MDDI serial encoder.
[0018] FIGs. 4A-B illustrate examples of signal skew.
[0019] FIG. 5 is a block diagram that illustrates an MDDI serial encoder according to an embodiment of the present invention.
[0020] FIG. 6 is a circuit diagram that illustrates an MDDI serial encoder according to another embodiment of the present invention.
[0021] FIG. 7 is an example timing diagram relating signals of the MDDI serial encoder of FIG. 6.
[0022] FIG. 8 is a circuit diagram that illustrates an MDDI serial encoder according to a further embodiment of the present invention.
[0023] FIG. 9 is an example timing diagram relating signals of the MDDI
serial encoder of FIG. 8.
[0024] The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.
DETAILED DESCRIPTION
100251 This specification discloses one or more embodiments that incorporate the features of this invention. The disclosed embodiment(s) merely exemplify the invention. The scope of the invention is not limited to the disclosed embodiment(s).
The invention is defined by the claims appended hereto.
100261 The embodiment(s) described, and references in the specification to "one embodiment", "an embodiment", "an example embodiment", etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
100271 Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. However, it should be appreciated that such descriptions are merely for convenience and that such actions in fact result from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc.
Mobile Display Digital Interface (MDDI) [0028] The Mobile Display Digital Interface (MDDI) is a cost-effective, low power consumption, transfer mechanism that enables very-high-speed serial data transfer over a short-range communication link between a host and a client.
[0029] In the following, examples of MDDI will be presented with respect to a camera module contained in an upper clamshell of a mobile phone. However, it would be apparent to persons skilled in the relevant art(s) that any module having functionally equivalent features to the camera module could be readily substituted and used in various embodiments of this invention.
[0030] Further, according to embodiments of the invention, an MDDI host may comprise one of several types of devices that can benefit from using the present invention. For example, the host could be a portable computer in the form of a handheld, laptop, or similar mobile computing device. It could also be a Personal Data Assistant (PDA), a paging device, or one of many wireless telephones or modems. Alternatively, the host could be a portable entertainment or presentation device such as a portable DVD or CD player, or a game playing device.
Furthermore, the host can reside as a host device or control element in a variety of other widely used or planned commercial products for which a high speed communication link with a client is desired. For example, a host could be used to transfer data at high rates from a video recording device to a storage based client for improved response, or to a high resolution larger screen for presentations. An appliance such as a refrigerator that incorporates an onboard inventory or computing system and/or Bluetooth connections to other household devices, can have improved display capabilities when operating in an internet or Bluetooth connected mode, or have reduced wiring needs for in-the-door displays (a client) and keypads or scanners (client) while the electronic computer or control systems (host) reside elsewhere in the cabinet. In general, those skilled in the art will appreciate the wide variety of modern electronic devices and appliances that may benefit from the use of this interface, as well as the ability to retrofit older devices with higher data rate transport of information utilizing limited numbers of conductors available in either newly added or existing connectors or cables.
At the same time, an MDDI client may comprise a variety of devices useful for presenting information to an end user, or presenting information from a user to the host.
For example, a micro-display incorporated in goggles or glasses, a projection device built into a hat or helmet, a small screen or even holographic element built into a vehicle, such as in a window or windshield, or various speaker, headphone, or sound systems for presenting high quality sound or music. Other presentation devices include projectors or projection devices used to present information for meetings, or for movies and television images. Other examples include the use of touch pads or sensitive devices, voice recognition input devices, security scanners, and so forth that may be called upon to transfer a significant amount of information from a device or system user with little actual "input" other than touch or sound from the user. In addition, docking stations for computers and car kits or desk-top kits and holders for wireless telephones may act as interface devices to end users or to other devices and equipment, and employ either clients (output or input devices such as mice) or hosts to assist in the transfer of data, especially where high speed networks are involved. However, those skilled in the art will readily recognize that the present invention is not limited to these devices, there being many other devices on the market, and proposed for use, that are intended to provide end users with high quality images and sound, either in terms of storage and transport or in terms of presentation at playback. The present invention is useful in increasing the data throughput between various elements or devices to accommodate the high data rates needed for realizing the desired user experience.
[0031] FIG. 1 is a block diagram that illustrates an example environment using an MDDI interface. In the example of FIG. 1, MDDI is used to interconnect modules across the hinge of a clamshell phone 100. It must be noted here that while certain embodiments of the present invention will be described in the context of specific examples, such as MDDI interconnections in a clamshell phone, this is done for illustration purposes only and should not be used to limit the present invention to such embodiments. As will be understood by a person skilled in the relevant art(s) based on the teachings herein, embodiments of the present invention may be used in other devices including any that may benefit from having MDDI
interconnections.
[0032] Referring to FIG. 1, a lower clamshell section 102 of clamshell phone 100 includes a Mobile Station Modem (MSM) baseband chip 104. MSM 104 is a digital baseband controller. An upper clamshell section 114 of clamshell phone 100 includes a Liquid Crystal Display (LCD) module 116 and a camera module 118.
[0033] Still referring to FIG. 1, an MDDI link 110 connects camera module 118 to MSM 104. Typically, an MDDI link controller is integrated into each of camera module 118 and MSM 104. In the example of FIG. 1, an MDDI Host 122 is integrated into camera module 112, while an MDDI Client 106 resides on the MSM
side of the MDDI link 110. Typically, the MDDI host is the master controller of the MDDI link. In the example of FIG. 1, pixel data from camera module 118 are received and formatted into MDDI packets by MDDI Host 122 before being transmitted onto MDDI link 110. MDDI client 106 receives the MDDI packets and re-converts them into pixel data of the same format as generated by camera module 118. The pixel data are then sent to an appropriate block in MSM 104 for processing.
[0034] Still referring to FIG. 1, an MDDI link 112 connects LCD module 116 to MSM 104. In the example of FIG. 1, MDDI link 112 interconnects an MDDI Host 108, integrated into MSM 104, and an MDDI Client 120 integrated into LCD
module 116. In the example of FIG. 1, display data generated by a graphics controller of MSM 104 are received and formatted into MDDI packets by MDDI Host 108 before being transmitted onto MDDI link 112. MDDI client 120 receives the MDDI
packets and re-converts them into display data for use by LCD module 116.
100351 FIG. 2 is a block diagram that illustrates MDDI link interconnection 110 according to the example of FIG. 1. As described above, one of the functions of MDDI link 110 is to transfer pixel data from camera module 118 to MSM 104.
Accordingly, in the embodiment of FIG. 2, a frame interface 206 connects camera module 118 to MDDI Host 122. The frame interface 206 serves to transfer pixel data from camera module 118 to MDDI Host 122.
100361 Typically, camera module 118 receives pixel data from a camera through a parallel interface, stores the pixel data, and then transfers it to MDDI Host 122 when the host is ready. MDDI Host 122 encapsulates the received pixel data into MDDI
packets. However, in order for MDDI Host 122 to be able to transmit the pixel data onto MDDI link 110, a serialization of the MDDI packets is necessary.
100371 In the embodiment of FIG. 2, a serializer module 202, integrated within MDDI Host 122, serves to serially shift out the MDDI packets onto MDDI link 110.
At the MSM end of MDDI link 110, a de-serializer module 204, integrated within MDDI client 106, re-constructs the MDDI packets from the serial data received over MDDI link 110. MDDI client 106 then removes the MDDI encapsulation and transfers the parallel pixel data through a frame interface 208 to an appropriate block of MSM 104.
MDDI Serial Encoder 100381 FIG. 3 is a circuit diagram that illustrates an MDDI serial encoder 300.
MDDI serial encoder 300 is described in more detail in U.S. Application No.
11/285,397, entitled "Double Data Rate Serial Encoder", filed November 23, 2005.
Serial encoder 300 includes a final data register stage, illustrated using flip-flops 320 and 322, a select input register stage, illustrated using flip-flops 314, 316, and 318, and a glitchless multiplexer circuitry 324.
[0039] The final data register stage flip-flops 320 and 322 receive data input signals 308 and 310, respectively. In one embodiment, data input signals 308 and 310 are each 4 bits. Accordingly, flip-flops 320 and 322 are each 4-bit flip-flops. In other embodiments, flip-flops 320 and 322 may be replaced with four 2-bit flip-flops or eight 1-bit flip-flops. As illustrated in FIG. 3, flip-flops 320 and 322 are D
flip-flops, but other types of flip-flops or registers may also be used as understood by a person skilled in the art based on the teachings herein. Flip-flops 320 and 322 are controlled by a clock signal 312 and update their outputs at every rising edge of clock signal 312.
[0040] The select input register stage flip-flops 314, 316, and 318 receive select input signals sel(2) 302, sel(1) 304, and sel(0) 306, respectively. Select input signals 302, 304, and 306 are typically provided by a counter and are used to select the input of multiplexer circuitry 324. In one embodiment, select signals 302, 304, and 306 are generated according to a Gray code sequence, which is known a priori by multiplexer circuitry 324, thereby allowing a glitchless multiplexer output.
Flip-flops 314, 316, and 318 are D flip-flops, but other types of flip-flops may also be used as understood by a person skilled in the art based on the teachings herein.
Flip-flops 314, 316, and 318 are also controlled by clock signal 312, with flip-flop 318 updating its output at rising edges of clock signal 312 and flip-flops 314 and 316 updating their outputs at falling edges of clock signal 312.
[0041] Multiplexer circuitry 324 receives data input signals from the final data register stage and input select signals from the select input register stage, and generates the output 334 of serial encoder 300. Multiplexer circuitry 324 generates a glitchless encoder output using a priori knowledge of the Gray code input select sequence. Multiplexer circuitry 324 includes four layers of logic 326, 328, 330, and 332 that separate the final data register stage (flip-flops 320 and 322) and the select input register stage (flip-flops 318, 320, and 322) from the encoder output 334. Logic layer 326 includes inverter circuitry on certain paths from the select input register stage to the encoder output. Logic layer 326 is coupled via an interconnect to logic layer 328, which includes a plurality of AND gates. In turn, logic layer 328 is coupled via an interconnect to logic layer 330. Logic layer 330 includes a plurality of OR gates, which provide the inputs of logic layer 332. Logic layer 332 includes an OR gate that provides the output 334 of the serial encoder.
[0042] It is noted that the four logic layers 326, 328, 330, and 332 of multiplexer circuitry 324 are based on combinatorial logic and are not driven by clock signals.
Accordingly, signal propagation delays on different paths from the final data register stage and/or the select input register stage to the encoder output may be different.
Further, signal propagation delays could vary according to temperature and/or process variations in the encoder circuitry, making them difficult to monitor and/or to compensate for.
[0043] Typically, having different signal propagation delays on paths to the encoder output results in what is known as "output skew", with the actual encoder output being skewed or distorted relative to a desired nominal output. Output skew may also result from the skewing of a single signal that contributes to the encoder output.
100441 FIGs. 4A-B illustrate examples of signal skew. FIG. 4A
illustrates skew in an example signal 400, whereby falling and/or rising edges may occur earlier or later than when they should ideally occur. FIG. 4B illustrates skew between two signals Output 1 and Output 2. Output 1 and Output 2 result from synchronized input signals 402 and 402 propagating through paths 406 and 408 respectively of exemplary circuit 414, with paths 406 and 408 having different signal propagation delays. The skew between signals Output 1 and Output 2, illustrated as "tsk"
in FIG.
4B, represents the time difference magnitude between signals Output 1 and Output 2, which ideally would occur simultaneously. Note that the skew between signals Output 1 and Output 2 could result in an output skew at output 412 of exemplary circuit 414.
[0045] In certain cases, output skew may cause a reduction in the maximum MDDI
link rate. It is evident therefore that output skew should be minimized.
Low Output Skew MDDI Serial Encoder [0046] According to the present invention, output skew is reduced by minimizing the effects of factors that contribute thereto. In one aspect, output skew is affected by the individual skew of each signal (from the final data register stage and/or the select input register stage) that contributes to the encoder output. In another aspect, output skew is proportional to the magnitudes of these individual signal skews, which, in turn, are proportional to the lengths of their respective signal paths (a function of the number of successive logic layers to reach the encoder output).
[0047] As such, output skew can be reduced by minimizing: (1) the number of signals (from the final data register stage and/or select input register stage) that contribute to the encoder output, and (2) the number of logic layers from the final data register stage and/or the select input register stage to the encoder output.
[0048] FIG. 5 is a block diagram that illustrates an MDDI serial encoder according to an embodiment of the present invention. Serial encoder 500 includes a non-glitchless multiplexer 506 and a synchronizing circuit 510.
[0049] Non-glitchless multiplexer 506 receives data input signal 504 and input select signals 502 and generates output signal 508. In an embodiment, data input signal 504 includes an 8-bit signal. In other embodiments, data input signal 504 includes two 4-bit signals, four 2-bit signals, or eight 1-bit signals. Input select signals 502 control multiplexer 506 to couple one of the received data input signals to the output of the multiplexer. Typically, the number, N, of input select signals 502 is such that 2N equals the number of data bits in signal 504. In FIG. 5, the number of input select signals 502 is 3, making multiplexer 506 an 8:1 multiplexer.
[0050] Since the output 508 of multiplexer 506 may be non-glitchless, serial encoder 500 can be significantly simplified. In one aspect, data bits in input signal 504 are allowed to switch at any time and not only when they are not being selected for output, as in a glitchless multiplexer. In another aspect, the input selection sequence carried by input select signals 502 no longer need to adhere to a Gray code sequence.
[0051] Accordingly, to generate a glitchless encoder output, a synchronizing circuit 510 is used to ensure that any glitches in output 508 are removed at encoder output 512. In one embodiment, synchronizing circuit 510 includes a clock-driven final data register stage that enables signals contributing to the encoder output to have minimal skew relative to each other. In addition, the final data register stage is a very small number of logic layers away from the encoder output, further reducing output skew.
[0052] FIG. 6 is a circuit diagram that illustrates an MDDI serial encoder 600 according to another embodiment of the present invention.
[0053] Serial encoder 600 includes a data register stage, illustrated using flip-flop 620, a select input register stage, illustrated using flip-flops 612, 614, and 616, a multiplexer 622, and a synchronizing circuit 626.
[0054] The data register stage flip-flop 620 receives data input signal 610. In one embodiment, data input signal 610 includes an 8-bit signal. Accordingly, flip-flop 620 is an 8-bit flip-flop. In other embodiments, flip-flop 620 may be replaced with two 4-bit flip-flops, four 2-bit flip-flops, or eight 1-bit flip-flops. As illustrated in FIG. 6, flip-flop 620 is a D flip-flop, but other types of flip-flops or registers may also be used as understood by a person skilled in the art based on the teachings herein.
[0055] The select input register stage flip-flops 612, 614, and 616 receive select input signals sel(2) 602, sel(1) 604, and sel(0) 606, respectively. Select input signals 602, 604, and 606 are typically provided by a counter and are used to select the input of multiplexer 622. Select signals 602, 604, and 606 need not adhere to any type of input selection sequence, such as a Gray code sequence, for example. Flip-flops 612, 614, and 616 are D flip-flops, but other types of flip-flops may also be used as understood by a person skilled in the art based on the teachings herein.
[0056] Multiplexer 622 receives data input signals from the data register stage and input select signals from the select input register stage, and generates output signal 624. In one embodiment, multiplexer 622 is an 8:1 multiplexer.
[0057] Multiplexer 622 is a non-glitchless multiplexer. In other words, glitches may occur in output 624 of multiplexer 622. Accordingly, output 624 of multiplexer is provided to a synchronizing circuit 626 to ensure that any glitches in output 624 are removed at encoder output 642.
[0058] Synchronizing circuit 626 includes a first XOR stage, illustrated using XOR
gates 628 and 630, a final data register stage, illustrated using flip-flops 632, 634, 636, and 638, and a final XOR stage, illustrated using XOR gate 640, to generate encoder output 642.
[0059] The first XOR stage gates 628 and 630 receive output signal 624 and feedback signals from flip-flops 636 and 634, respectively. The outputs of XOR gates 628 and 630 are respectively received by flip-flops 632, 634 and 636, 638. Flip-flops 632, 634, 636, and 638 are controlled by a clock signal clk, with flip-flops 632 and 634 updating outputs at rising edges of the clock signal and flip-flops 636 and updating outputs at falling edges of the clock signal.
[0060] Flip-flops 634 and 636 are feedback flip-flops of the final data register stage having their outputs cross-coupled to XOR gates 628 and 630 of the first XOR
stage.
In other embodiments, the feedback signals to XOR gates 628 and 630 are provided from the outputs of flip-flops 638 and 632 respectively, with flip-flops 634 and 636 eliminated from the final data register stage. A more stable design, however, is achieved by using flip-flops 634 and 636 to provide the feedback signals to the first XOR stage. This reduces any additional routing of the outputs of flip-flops 632 and 638, which then need to only be input into the final XOR stage of synchronizing circuit 626.
[0061] The final XOR stage of synchronizing circuit 626 includes a single XOR gate 640, which receives the outputs of flip-flops 632 and 638 and outputs encoder output 642. Encoder output 642 is a glitchless output with low output skew.
[0062] It is noted that in serial encoder 600, a single layer of logic separates the final data register stage from the encoder output. Accordingly, the individual skew of signals contributing to the encoder output remains very low. Further, it is noted that only two signals from the final data register stage (outputs of flip-flops 632 and 638) contribute to encoder output 642, further reducing output skew. The reduced number of paths from the final register stage to the encoder output also simplifies output skew analysis.
100631 FIG. 8 is a circuit diagram that illustrates an MDDI serial encoder 800 according to a further embodiment of the present invention. MDDI serial encoder 800 is similar in several respects to MDDI serial encoder 600 of FIG. 6, but employs a different synchronizing circuit implementation 812. It is noted that, in practice, the synchronizing circuit is equivalent to a dual edge flip-flop, and accordingly, any implementation of a dual edge flip-flop or functionally equivalent circuitry may be used for the synchronizing circuit according to embodiments of the present invention.
100641 In FIG. 8, synchronizing circuit 812 includes a final data register stage, illustrated using flip flops 804 and 806, and a multiplexer 808. Flip flops 804 and 806 receive output signal 624 of multiplexer 622 and are controlled by clock signal 802, with flip flop 804 updating its output at rising edges of clock signal 802 and flip flop 806 updating its output at falling edges of clock signal 802. The outputs of flip flops 804 and 806 subsequently form inputs to multiplexer 808. Multiplexer 808 is also controlled by clock signal 802, with the output of flip flop 804 being output from multiplexer 808 when the clock signal 802 is high and the output of flip flop being output from multiplexer 808 when the clock signal 802 is low, to generate the encoder output 810. It is noted that, in embodiment 800, the encoder output has a race condition on clock signal 802. This race condition is a result of a rising or falling edge in clock signal 802 causing the currently selected input to multiplexer 808 to change. The encoder output 810 is glitchless only if a rising or falling edge of clock signal 802 has selected the other input of the multiplexer 808 as the encoder output 810 before the current input changes. As an example, when clock signal is low, the output of flip flop 806 is being output from multiplexer 808 as encoder output 810. At a rising edge of the clock signal 802, the output of flip flop 806 will update to a new state while at the same time the output of flip flop 804 is selected as the output of multiplexer 808 as encoder output 810. To avoid glitches on encoder output 810, the delay from clock signal 802 through multiplexer 808 to the encoder output 810 must be less than the delay from clock signal 802 through flip flops 804 or 806 to multiplexer 808. As long as this timing condition is met, encoder output 810 is a glitchless output with low output skew.
[0065] It is also noted that in serial encoder 800, a single layer of logic separates the final data register stage from the encoder output with only two signals from the final data register stage contributing to encoder output 810, thereby resulting in a reduced output skew and simplified output skew analysis.
Example Timing Diagrams [0066] FIG. 7 is an example timing diagram relating signals of MDDI
serial encoder 600 of FIG. 6. In this example diagram, the select inputs transitions, illustrated as signal sel[2:0] in FIG. 7, are in accordance with a Gray code sequence as typically required for MDDI encoders with glitchless multiplexer. Accordingly, multiplexer 622 of FIG. 6 operates identically to a glitchless multiplexer, but without the glitch free output requirement. Note that the select inputs sequence in FIG. 7 is an exemplary one and that other select inputs sequences may also be used.
[0067] Signal din[7:0] in FIG. 7 corresponds to data input signal 610 in FIG. 6. An exemplary sequence of signal din[7:0] is provided in FIG. 7.
[0068] Signal din_reg[7:0] corresponds to signal din_reg[7:0] illustrated in FIG. 6, and can be generated from signal din[7:0] according to signal data_en in FIG.
7. An exemplary sequence of signal din_reg[7:0] is provided in FIG. 7.
[0069] Signal desired_data_out corresponds to signal 624 in FIG. 6.
[0070] Signals out_rise and out fall correspond to the outputs of flip-flops 632 and 638, respectively. Note that out_rise = (desired_data_out XOR out fall) and that out_fall = (desired_data_out XOR out_rise). Also note that signal dout =
out_rise XOR out_fall. Accordingly, either of the two final output registers can drive the desired_data_out value to dout by holding or inverting its output. Signal dout is equivalent to signal desired_data_out but is delayed by 1/2 clock cycle.
[0071] FIG. 9 is an example timing diagram relating signals of MDDI serial encoder 800 of FIG. 8. Similar to the example timing diagram of FIG. 7, the select inputs transitions, illustrated as sel[2:0] in FIG. 9, are in accordance with a Gray code sequence as typically required for MDDI encoders with glitchless multiplexer.
Note, however, that the select inputs sequence illustrated in FIG. 9 is only exemplary and that other select inputs sequences may also be used.
[0072] Signal (11147:0] in FIG. 9 corresponds to data input signal 610 in FIG. 8. An exemplary sequence of signal din[7:01 is provided in FIG. 9.
[0073] Signal din_reg[7:0] corresponds to the output of flip-flop 620 in FIG. 8. An exemplary sequence of signal din_reg[7:0] is provided in FIG. 9.
[0074] Signal desired_data_out corresponds to signal 624 in FIG. 8.
[0075] Signals pos_reg and neg_reg correspond to the outputs of flip-flops 804 and 806, respectively, in FIG. 8.
[0076] Signal dout corresponds to encoder output dout 810 in FIG. 8. Note that dout is equivalent to desired_data_out signal, but is delayed by 1 clock cycle, with 1/2 clock cycle delay due to flip-flops 804 and 806 and lh clock cycle delay due to multiplexer 808.
Conclusion =
[0077] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to persons skilled in the relevant art that various changes in form and detail can be made therein without departing from the scope of the claims. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims.
Claims (24)
1. A serial encoder comprising:
means for storing a plurality of data input bits;
means for storing a plurality of select input bits;
means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage, wherein the output of said serial outputting means is coupled to a data input of the clock-driven register stage, and wherein said register stage is separated by a single logic layer from the serial encoder output, thereby resulting in a low output skew of the encoder.
means for storing a plurality of data input bits;
means for storing a plurality of select input bits;
means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage, wherein the output of said serial outputting means is coupled to a data input of the clock-driven register stage, and wherein said register stage is separated by a single logic layer from the serial encoder output, thereby resulting in a low output skew of the encoder.
2. The serial encoder according to claim 1, wherein the means for serially outputting comprise a multiplexer having a plurality of data inputs, a plurality of select inputs, and an output;
the means for storing the plurality of data input bits comprise a plurality of data input flip-flops coupled to the data inputs of the multiplexer;
the means for storing the plurality of select input bits comprise a plurality of select input flip-flops coupled to the select inputs of the multiplexer; and the means for eliminating comprise a synchronizing circuit coupled to the output of the multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage, and the final data register stage is separated by a single logic layer from the output of the serial encoder, thereby resulting in a low output skew of the encoder, wherein the output of the multiplexer is coupled to a data input of the final data register stage, and wherein the synchronizing circuit substantially eliminates any output glitches from the output of the multiplexer.
the means for storing the plurality of data input bits comprise a plurality of data input flip-flops coupled to the data inputs of the multiplexer;
the means for storing the plurality of select input bits comprise a plurality of select input flip-flops coupled to the select inputs of the multiplexer; and the means for eliminating comprise a synchronizing circuit coupled to the output of the multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage, and the final data register stage is separated by a single logic layer from the output of the serial encoder, thereby resulting in a low output skew of the encoder, wherein the output of the multiplexer is coupled to a data input of the final data register stage, and wherein the synchronizing circuit substantially eliminates any output glitches from the output of the multiplexer.
3. The serial encoder according to claim 2, wherein the multiplexer has eight data inputs and three select inputs.
4. The serial encoder according to claim 2, wherein the multiplexer is a non-glitchless multiplexer.
5. The serial encoder according to claim 2, wherein the data input flip-flops and the select input flip-flops are D flip-flops.
6. The serial encoder according to claim 2, wherein the select inputs of the multiplexer are provided by a counter according to a clock signal.
7. The serial encoder according to claim 6, wherein the multiplexer outputs a bit at every edge of the clock signal.
8. The serial encoder according to claim 2, wherein the final data register stage is clock-driven.
9. The serial encoder according to claim 2, wherein the encoder receives a parallel data input and serially outputs the data input onto a serial communications link.
10. The serial encoder according to claim 9, wherein the serial communications link is a Mobile Display Digital Interface (MDDI) link.
11. The serial encoder according to claim 2, wherein the synchronizing circuit is implemented using any dual edge flip-flop.
12. The serial encoder according to claim 1, wherein the clock drive register stage outputs two signals, and wherein the serial encoder output is determined by selecting one of the two signals, such that the serial encoder output is solely determined by the two signals from said register stage, thereby resulting in a low output skew of the encoder.
13. The serial encoder according to claim 12, wherein said serial outputting means outputs a bit at every edge of a clock signal, thereby making the serial encoder a double data rate encoder.
14. A serial encoder, comprising:
means for storing a plurality of data input bits;
means for storing a plurality of select input bits;
means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage which outputs two signals and means for selecting one of the two signals as the serial encoder output, and wherein the serial encoder output is solely determined by two signals from said register stage, thereby resulting in a low output skew of the encoder, wherein the output of said serial outputting means is coupled to a data input of the clock-driven register stage.
means for storing a plurality of data input bits;
means for storing a plurality of select input bits;
means for serially outputting the plurality of data input bits according to an input selection sequence generated by the plurality of select input bits; and means for eliminating glitches from an output of said serial outputting means, thereby generating a glitchless serial encoder output, wherein said means for eliminating glitches includes a clock-driven register stage which outputs two signals and means for selecting one of the two signals as the serial encoder output, and wherein the serial encoder output is solely determined by two signals from said register stage, thereby resulting in a low output skew of the encoder, wherein the output of said serial outputting means is coupled to a data input of the clock-driven register stage.
15. The serial encoder according to claim 14, wherein the means for serially outputting comprise a first multiplexer having a plurality of data inputs, a plurality of select inputs, and an output, and the means for storing the plurality of data input bits comprise a plurality of data input flip-flops coupled to the data inputs of the first multiplexer;
the means for storing the plurality of select input bits comprise a plurality of select input flip-flops coupled to the select inputs of the first multiplexer;
and the means for eliminating comprising a synchronizing circuit coupled to the output of the first multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage which outputs two signals and a second multiplexer for selecting one of the two signals as the serial encoder output.
the means for storing the plurality of select input bits comprise a plurality of select input flip-flops coupled to the select inputs of the first multiplexer;
and the means for eliminating comprising a synchronizing circuit coupled to the output of the first multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage which outputs two signals and a second multiplexer for selecting one of the two signals as the serial encoder output.
16. The serial encoder according to claim 15, wherein the first multiplexer has eight data inputs and three select inputs.
17. The serial encoder according to claim 15, wherein the first multiplexer is a non-glitchless multiplexer.
18. The serial encoder according to claim 15, wherein the data input flip-flops and the select input flip-flops are D flip-flops.
19. The serial encoder according to claim 15, wherein the select inputs of the first multiplexer are provided by a counter according to a clock signal.
20. The serial encoder according to claim 15, wherein the first multiplexer outputs a bit at every edge of the clock signal.
21. The serial encoder according to claim 15, wherein the final data register stage is clock-driven.
22. The serial encoder according to claim 15, wherein the encoder receives a parallel data input and serially outputs the data input onto a serial communications link.
23. The serial encoder according to claim 15, wherein said serial outputting means outputs a bit at every edge of a clock signal, thereby making the serial encoder a double data rate encoder.
24. A method of serial encoding, comprising:
providing a first multiplexer having a plurality of data inputs, a plurality of select inputs, and an output;
providing a plurality of data input flip-flops coupled to the data inputs of the first multiplexer;
providing a plurality of select input flip-flops coupled to the select inputs of the first multiplexer; and providing a synchronizing circuit coupled to the output of the first multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage which outputs two signals and a second multiplexer for selecting one of the two signals as the serial encoder output, thereby resulting in a low output skew of the encoder, wherein the output of said first multiplexer is coupled to a data input of the final data register stage, and employing the synchronizing circuit to substantially eliminate output glitches from the output of the first multiplexer.
providing a first multiplexer having a plurality of data inputs, a plurality of select inputs, and an output;
providing a plurality of data input flip-flops coupled to the data inputs of the first multiplexer;
providing a plurality of select input flip-flops coupled to the select inputs of the first multiplexer; and providing a synchronizing circuit coupled to the output of the first multiplexer and providing an output of the serial encoder, wherein the synchronizing circuit comprises a final data register stage which outputs two signals and a second multiplexer for selecting one of the two signals as the serial encoder output, thereby resulting in a low output skew of the encoder, wherein the output of said first multiplexer is coupled to a data input of the final data register stage, and employing the synchronizing circuit to substantially eliminate output glitches from the output of the first multiplexer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/463,129 | 2006-08-08 | ||
| US11/463,129 US8723705B2 (en) | 2004-11-24 | 2006-08-08 | Low output skew double data rate serial encoder |
| PCT/US2007/075127 WO2008021749A1 (en) | 2006-08-08 | 2007-08-02 | Low output skew double data rate serial encoder |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2658561A1 CA2658561A1 (en) | 2008-02-21 |
| CA2658561C true CA2658561C (en) | 2016-08-16 |
Family
ID=38823562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2658561A Expired - Fee Related CA2658561C (en) | 2006-08-08 | 2007-08-02 | Low output skew double data rate serial encoder |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US8723705B2 (en) |
| EP (2) | EP2055008B1 (en) |
| JP (1) | JP5038418B2 (en) |
| KR (1) | KR101096932B1 (en) |
| CN (1) | CN101502000B (en) |
| BR (1) | BRPI0714865B1 (en) |
| CA (1) | CA2658561C (en) |
| ES (2) | ES2460723T3 (en) |
| RU (1) | RU2009108263A (en) |
| WO (1) | WO2008021749A1 (en) |
Families Citing this family (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6760772B2 (en) * | 2000-12-15 | 2004-07-06 | Qualcomm, Inc. | Generating and implementing a communication protocol and interface for high data rate signal transfer |
| US8812706B1 (en) * | 2001-09-06 | 2014-08-19 | Qualcomm Incorporated | Method and apparatus for compensating for mismatched delays in signals of a mobile display interface (MDDI) system |
| CN103220282B (en) * | 2003-06-02 | 2016-05-25 | 高通股份有限公司 | Generate and implement one for more signal protocol and the interface of High Data Rate |
| EP2363989B1 (en) * | 2003-08-13 | 2018-09-19 | Qualcomm Incorporated | A signal interface for higher data rates |
| RU2369033C2 (en) * | 2003-09-10 | 2009-09-27 | Квэлкомм Инкорпорейтед | High-speed data transmission interface |
| CN1894931A (en) * | 2003-10-15 | 2007-01-10 | 高通股份有限公司 | High data rate interface |
| RU2331160C2 (en) | 2003-10-29 | 2008-08-10 | Квэлкомм Инкорпорейтед | Interface with high speed of data transmission |
| US8606946B2 (en) * | 2003-11-12 | 2013-12-10 | Qualcomm Incorporated | Method, system and computer program for driving a data signal in data interface communication data link |
| CA2546971A1 (en) * | 2003-11-25 | 2005-06-09 | Qualcomm Incorporated | High data rate interface with improved link synchronization |
| CA2731363C (en) * | 2003-12-08 | 2013-10-08 | Qualcomm Incorporated | High data rate interface with improved link synchronization |
| CN101827103B (en) * | 2004-03-10 | 2012-07-04 | 高通股份有限公司 | High data rate interface apparatus and method |
| KR101245962B1 (en) * | 2004-03-17 | 2013-03-21 | 퀄컴 인코포레이티드 | High data rate interface apparatus and method |
| WO2005096594A1 (en) * | 2004-03-24 | 2005-10-13 | Qualcomm Incorporated | High data rate interface apparatus and method |
| US8650304B2 (en) * | 2004-06-04 | 2014-02-11 | Qualcomm Incorporated | Determining a pre skew and post skew calibration data rate in a mobile display digital interface (MDDI) communication system |
| CA2569106C (en) * | 2004-06-04 | 2013-05-21 | Qualcomm Incorporated | High data rate interface apparatus and method |
| US8539119B2 (en) * | 2004-11-24 | 2013-09-17 | Qualcomm Incorporated | Methods and apparatus for exchanging messages having a digital data interface device message format |
| US8692838B2 (en) * | 2004-11-24 | 2014-04-08 | Qualcomm Incorporated | Methods and systems for updating a buffer |
| US8667363B2 (en) * | 2004-11-24 | 2014-03-04 | Qualcomm Incorporated | Systems and methods for implementing cyclic redundancy checks |
| US8699330B2 (en) | 2004-11-24 | 2014-04-15 | Qualcomm Incorporated | Systems and methods for digital data transmission rate control |
| US20060161691A1 (en) * | 2004-11-24 | 2006-07-20 | Behnam Katibian | Methods and systems for synchronous execution of commands across a communication link |
| US8873584B2 (en) | 2004-11-24 | 2014-10-28 | Qualcomm Incorporated | Digital data interface device |
| US8692839B2 (en) * | 2005-11-23 | 2014-04-08 | Qualcomm Incorporated | Methods and systems for updating a buffer |
| US8730069B2 (en) * | 2005-11-23 | 2014-05-20 | Qualcomm Incorporated | Double data rate serial encoder |
| JP2014052552A (en) | 2012-09-07 | 2014-03-20 | Sharp Corp | Memory controller, portable terminal, memory control program and computer readable recording medium |
| JP2014052551A (en) | 2012-09-07 | 2014-03-20 | Sharp Corp | Memory controller, portable terminal, memory control program and computer readable recording medium |
| JP2014052548A (en) | 2012-09-07 | 2014-03-20 | Sharp Corp | Memory controller, portable terminal, memory control program and computer readable recording medium |
| JP2014052902A (en) | 2012-09-07 | 2014-03-20 | Sharp Corp | Memory controller, portable terminal, memory control program and computer readable recording medium |
| JP6199070B2 (en) | 2013-04-26 | 2017-09-20 | シャープ株式会社 | Memory control device and portable terminal |
| KR20150040540A (en) * | 2013-10-07 | 2015-04-15 | 에스케이하이닉스 주식회사 | Semiconductor dvice and semiconductor systems including the same |
| KR20160112143A (en) | 2015-03-18 | 2016-09-28 | 삼성전자주식회사 | Electronic device and method for updating screen of display panel thereof |
| CN112290922A (en) * | 2020-11-09 | 2021-01-29 | 无锡拍字节科技有限公司 | Parallel input and serial output circuit and memory using the same |
Family Cites Families (437)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7274652B1 (en) | 2000-06-02 | 2007-09-25 | Conexant, Inc. | Dual packet configuration for wireless communications |
| US3594304A (en) | 1970-04-13 | 1971-07-20 | Sun Oil Co | Thermal liquefaction of coal |
| US4042783A (en) | 1976-08-11 | 1977-08-16 | International Business Machines Corporation | Method and apparatus for byte and frame synchronization on a loop system coupling a CPU channel to bulk storage devices |
| US4393444A (en) | 1980-11-06 | 1983-07-12 | Rca Corporation | Memory addressing circuit for converting sequential input data to interleaved output data sequence using multiple memories |
| US4363123A (en) | 1980-12-01 | 1982-12-07 | Northern Telecom Limited | Method of and apparatus for monitoring digital transmission systems in which line transmission errors are detected |
| JPS57136833A (en) * | 1981-02-17 | 1982-08-24 | Sony Corp | Time-division multiplex data transmitting method |
| US4660096A (en) | 1984-12-11 | 1987-04-21 | Rca Corporation | Dividing high-resolution-camera video signal response into sub-image blocks individually raster scanned |
| DE3531809A1 (en) * | 1985-09-06 | 1987-03-26 | Kraftwerk Union Ag | CATALYST MATERIAL FOR REDUCING NITROGEN OXIDES |
| US4769761A (en) | 1986-10-09 | 1988-09-06 | International Business Machines Corporation | Apparatus and method for isolating and predicting errors in a local area network |
| JPS63226762A (en) | 1987-03-16 | 1988-09-21 | Hitachi Ltd | Data processing system |
| US4764805A (en) | 1987-06-02 | 1988-08-16 | Eastman Kodak Company | Image transmission system with line averaging preview mode using two-pass block-edge interpolation |
| US4821296A (en) * | 1987-08-26 | 1989-04-11 | Bell Communications Research, Inc. | Digital phase aligner with outrigger sampling |
| US5227783A (en) | 1987-10-13 | 1993-07-13 | The Regents Of New Mexico State University | Telemetry apparatus and method with digital to analog converter internally integrated within C.P.U. |
| US5155590A (en) | 1990-03-20 | 1992-10-13 | Scientific-Atlanta, Inc. | System for data channel level control |
| US4891805A (en) | 1988-06-13 | 1990-01-02 | Racal Data Communications Inc. | Multiplexer with dynamic bandwidth allocation |
| US5167035A (en) | 1988-09-08 | 1992-11-24 | Digital Equipment Corporation | Transferring messages between nodes in a network |
| US5136717A (en) * | 1988-11-23 | 1992-08-04 | Flavors Technology Inc. | Realtime systolic, multiple-instruction, single-data parallel computer system |
| US5079693A (en) | 1989-02-28 | 1992-01-07 | Integrated Device Technology, Inc. | Bidirectional FIFO buffer having reread and rewrite means |
| US6014705A (en) * | 1991-10-01 | 2000-01-11 | Intermec Ip Corp. | Modular portable data processing terminal having a higher layer and lower layer partitioned communication protocol stack for use in a radio frequency communications network |
| US5224213A (en) * | 1989-09-05 | 1993-06-29 | International Business Machines Corporation | Ping-pong data buffer for transferring data from one data bus to another data bus |
| US5495482A (en) * | 1989-09-29 | 1996-02-27 | Motorola Inc. | Packet transmission system and method utilizing both a data bus and dedicated control lines |
| US5543939A (en) | 1989-12-28 | 1996-08-06 | Massachusetts Institute Of Technology | Video telephone systems |
| US5138616A (en) | 1990-03-19 | 1992-08-11 | The United States Of America As Represented By The Secretary Of The Army | Continuous on-line link error rate detector utilizing the frame bit error rate |
| US5111455A (en) * | 1990-08-24 | 1992-05-05 | Avantek, Inc. | Interleaved time-division multiplexor with phase-compensated frequency doublers |
| US5131012A (en) | 1990-09-18 | 1992-07-14 | At&T Bell Laboratories | Synchronization for cylic redundancy check based, broadband communications network |
| GB2249460B (en) | 1990-09-19 | 1994-06-29 | Intel Corp | Network providing common access to dissimilar hardware interfaces |
| GB2250668B (en) | 1990-11-21 | 1994-07-20 | Apple Computer | Tear-free updates of computer graphical output displays |
| IL100213A (en) | 1990-12-07 | 1995-03-30 | Qualcomm Inc | CDMA microcellular telephone system and distributed antenna system therefor |
| US5359595A (en) | 1991-01-09 | 1994-10-25 | Rockwell International Corporation | Skywave adaptable network transceiver apparatus and method using a stable probe and traffic protocol |
| US5345542A (en) | 1991-06-27 | 1994-09-06 | At&T Bell Laboratories | Proportional replication mapping system |
| US5231636A (en) | 1991-09-13 | 1993-07-27 | National Semiconductor Corporation | Asynchronous glitchless digital MUX |
| EP0606396B1 (en) * | 1991-10-01 | 2002-06-12 | Norand Corporation | A radio frequency local area network |
| US5396636A (en) | 1991-10-21 | 1995-03-07 | International Business Machines Corporation | Remote power control via data link |
| US5751445A (en) | 1991-11-11 | 1998-05-12 | Canon Kk | Image transmission system and terminal device |
| CA2064541C (en) | 1992-03-31 | 1998-09-15 | Thomas A. Gray | Cycling error count for link maintenance |
| US5331642A (en) | 1992-09-01 | 1994-07-19 | International Business Machines Corporation | Management of FDDI physical link errors |
| JP3305769B2 (en) | 1992-09-18 | 2002-07-24 | 株式会社東芝 | Communication device |
| JPH06124147A (en) | 1992-10-13 | 1994-05-06 | Sanyo Electric Co Ltd | Information processor |
| GB9222282D0 (en) | 1992-10-22 | 1992-12-09 | Hewlett Packard Co | Monitoring network status |
| US5513185A (en) * | 1992-11-23 | 1996-04-30 | At&T Corp. | Method and apparatus for transmission link error rate monitoring |
| US5867501A (en) * | 1992-12-17 | 1999-02-02 | Tandem Computers Incorporated | Encoding for communicating data and commands |
| US5619650A (en) | 1992-12-31 | 1997-04-08 | International Business Machines Corporation | Network processor for transforming a message transported from an I/O channel to a network by adding a message identifier and then converting the message |
| GB9304638D0 (en) | 1993-03-06 | 1993-04-21 | Ncr Int Inc | Wireless data communication system having power saving function |
| JPH06332664A (en) | 1993-03-23 | 1994-12-02 | Toshiba Corp | Display control system |
| US5418452A (en) * | 1993-03-25 | 1995-05-23 | Fujitsu Limited | Apparatus for testing integrated circuits using time division multiplexing |
| WO1994024200A1 (en) | 1993-04-16 | 1994-10-27 | Akzo Nobel N.V. | Liquid stabilizer comprising metal soap and solubilized metal perchlorate |
| JP3197679B2 (en) | 1993-04-30 | 2001-08-13 | 富士写真フイルム株式会社 | Photography system and method |
| US5519830A (en) * | 1993-06-10 | 1996-05-21 | Adc Telecommunications, Inc. | Point-to-multipoint performance monitoring and failure isolation system |
| JP2768621B2 (en) * | 1993-06-25 | 1998-06-25 | 沖電気工業株式会社 | Decoding apparatus for convolutional code transmitted in a distributed manner |
| US5477534A (en) * | 1993-07-30 | 1995-12-19 | Kyocera Corporation | Acoustic echo canceller |
| US5430486A (en) | 1993-08-17 | 1995-07-04 | Rgb Technology | High resolution video image transmission and storage |
| US5426694A (en) | 1993-10-08 | 1995-06-20 | Excel, Inc. | Telecommunication switch having programmable network protocols and communications services |
| US5490247A (en) | 1993-11-24 | 1996-02-06 | Intel Corporation | Video subsystem for computer-based conferencing system |
| US5510832A (en) | 1993-12-01 | 1996-04-23 | Medi-Vision Technologies, Inc. | Synthesized stereoscopic imaging system and method |
| US5565957A (en) | 1993-12-27 | 1996-10-15 | Nikon Corporation | Camera |
| US5724536A (en) | 1994-01-04 | 1998-03-03 | Intel Corporation | Method and apparatus for blocking execution of and storing load operations during their execution |
| US5844606A (en) | 1994-03-03 | 1998-12-01 | Fuji Photo Film Co., Ltd. | Videocamera having a multiconnector connectable to a variety of accessories |
| JP2790034B2 (en) | 1994-03-28 | 1998-08-27 | 日本電気株式会社 | Non-operational memory update method |
| US5483185A (en) * | 1994-06-09 | 1996-01-09 | Intel Corporation | Method and apparatus for dynamically switching between asynchronous signals without generating glitches |
| JP3329076B2 (en) | 1994-06-27 | 2002-09-30 | ソニー株式会社 | Digital signal transmission method, digital signal transmission device, digital signal reception method, and digital signal reception device |
| US5560022A (en) | 1994-07-19 | 1996-09-24 | Intel Corporation | Power management coordinator system and interface |
| US5748891A (en) | 1994-07-22 | 1998-05-05 | Aether Wire & Location | Spread spectrum localizers |
| KR100370665B1 (en) | 1994-07-25 | 2004-07-19 | 지멘스 악티엔게젤샤프트 | Connection and control method of video phone communication |
| US5664948A (en) | 1994-07-29 | 1997-09-09 | Seiko Communications Holding N.V. | Delivery of data including preloaded advertising data |
| US5733131A (en) | 1994-07-29 | 1998-03-31 | Seiko Communications Holding N.V. | Education and entertainment device with dynamic configuration and operation |
| JP3592376B2 (en) | 1994-08-10 | 2004-11-24 | 株式会社アドバンテスト | Time interval measuring device |
| KR100188990B1 (en) | 1994-09-27 | 1999-06-01 | 이리마지리 쇼우이치로 | Data transfer device and video game apparatus using the device |
| US5559459A (en) | 1994-12-29 | 1996-09-24 | Stratus Computer, Inc. | Clock signal generation arrangement including digital noise reduction circuit for reducing noise in a digital clocking signal |
| FR2729528A1 (en) | 1995-01-13 | 1996-07-19 | Suisse Electronique Microtech | Digital multiplexer circuit e.g. for clock control system |
| GB2298109B (en) | 1995-02-14 | 1999-09-01 | Nokia Mobile Phones Ltd | Data interface |
| US5530704A (en) | 1995-02-16 | 1996-06-25 | Motorola, Inc. | Method and apparatus for synchronizing radio ports in a commnuication system |
| US5646947A (en) | 1995-03-27 | 1997-07-08 | Westinghouse Electric Corporation | Mobile telephone single channel per carrier superframe lock subsystem |
| US6117681A (en) | 1995-03-29 | 2000-09-12 | Bavarian Nordic Research Inst. A/S | Pseudotyped retroviral particles |
| US6400392B1 (en) * | 1995-04-11 | 2002-06-04 | Matsushita Electric Industrial Co., Ltd. | Video information adjusting apparatus, video information transmitting apparatus and video information receiving apparatus |
| US5521907A (en) * | 1995-04-25 | 1996-05-28 | Visual Networks, Inc. | Method and apparatus for non-intrusive measurement of round trip delay in communications networks |
| SE506540C2 (en) | 1995-06-13 | 1998-01-12 | Ericsson Telefon Ab L M | Synchronization of data transfer via a bidirectional link |
| US5963564A (en) | 1995-06-13 | 1999-10-05 | Telefonaktiebolaget Lm Ericsson | Synchronizing the transmission of data via a two-way link |
| US6055247A (en) | 1995-07-13 | 2000-04-25 | Sony Corporation | Data transmission method, data transmission apparatus and data transmission system |
| JPH0936871A (en) | 1995-07-17 | 1997-02-07 | Sony Corp | Data transmission system and data transmission method |
| US5604450A (en) | 1995-07-27 | 1997-02-18 | Intel Corporation | High speed bidirectional signaling scheme |
| JPH0955667A (en) * | 1995-08-10 | 1997-02-25 | Mitsubishi Electric Corp | Multiplexer and demultiplexer |
| US5742840A (en) | 1995-08-16 | 1998-04-21 | Microunity Systems Engineering, Inc. | General purpose, multiple precision parallel operation, programmable media processor |
| JPH11503258A (en) * | 1995-09-19 | 1999-03-23 | マイクロチップ テクノロジー インコーポレイテッド | Microcontroller wake-up function with digitally programmable threshold |
| US5748642A (en) | 1995-09-25 | 1998-05-05 | Credence Systems Corporation | Parallel processing integrated circuit tester |
| US5818255A (en) | 1995-09-29 | 1998-10-06 | Xilinx, Inc. | Method and circuit for using a function generator of a programmable logic device to implement carry logic functions |
| US5732352A (en) | 1995-09-29 | 1998-03-24 | Motorola, Inc. | Method and apparatus for performing handoff in a wireless communication system |
| US5550489A (en) | 1995-09-29 | 1996-08-27 | Quantum Corporation | Secondary clock source for low power, fast response clocking |
| US5751951A (en) * | 1995-10-30 | 1998-05-12 | Mitsubishi Electric Information Technology Center America, Inc. | Network interface |
| TW316965B (en) | 1995-10-31 | 1997-10-01 | Cirrus Logic Inc | |
| US5958006A (en) | 1995-11-13 | 1999-09-28 | Motorola, Inc. | Method and apparatus for communicating summarized data |
| US7003796B1 (en) * | 1995-11-22 | 2006-02-21 | Samsung Information Systems America | Method and apparatus for recovering data stream clock |
| US5790551A (en) | 1995-11-28 | 1998-08-04 | At&T Wireless Services Inc. | Packet data transmission using dynamic channel assignment |
| US5844918A (en) | 1995-11-28 | 1998-12-01 | Sanyo Electric Co., Ltd. | Digital transmission/receiving method, digital communications method, and data receiving apparatus |
| US6865610B2 (en) | 1995-12-08 | 2005-03-08 | Microsoft Corporation | Wire protocol for a media server system |
| EP0781068A1 (en) | 1995-12-20 | 1997-06-25 | International Business Machines Corporation | Method and system for adaptive bandwidth allocation in a high speed data network |
| JP3427149B2 (en) | 1996-01-26 | 2003-07-14 | 三菱電機株式会社 | Decoding circuit for coded signal, synchronization control method thereof, synchronization detection circuit and synchronization detection method |
| US5903281A (en) | 1996-03-07 | 1999-05-11 | Powertv, Inc. | List controlled video operations |
| US6243596B1 (en) | 1996-04-10 | 2001-06-05 | Lextron Systems, Inc. | Method and apparatus for modifying and integrating a cellular phone with the capability to access and browse the internet |
| US5815507A (en) | 1996-04-15 | 1998-09-29 | Motorola, Inc. | Error detector circuit for digital receiver using variable threshold based on signal quality |
| US6130602A (en) | 1996-05-13 | 2000-10-10 | Micron Technology, Inc. | Radio frequency data communications device |
| JPH09307457A (en) | 1996-05-14 | 1997-11-28 | Sony Corp | Parallel/serial conversion circuit |
| US5982362A (en) | 1996-05-30 | 1999-11-09 | Control Technology Corporation | Video interface architecture for programmable industrial control systems |
| US5983261A (en) | 1996-07-01 | 1999-11-09 | Apple Computer, Inc. | Method and apparatus for allocating bandwidth in teleconferencing applications using bandwidth control |
| GB9614561D0 (en) * | 1996-07-11 | 1996-09-04 | 4Links Ltd | Communication system with improved code |
| US6298387B1 (en) | 1996-07-12 | 2001-10-02 | Philips Electronics North America Corp | System for detecting a data packet in a bitstream by storing data from the bitstream in a buffer and comparing data at different locations in the buffer to predetermined data |
| KR100221028B1 (en) | 1996-07-23 | 1999-09-15 | 윤종용 | Graphic accelerator and memory-prefetching method of it |
| US6185601B1 (en) * | 1996-08-02 | 2001-02-06 | Hewlett-Packard Company | Dynamic load balancing of a network of client and server computers |
| US6886035B2 (en) * | 1996-08-02 | 2005-04-26 | Hewlett-Packard Development Company, L.P. | Dynamic load balancing of a network of client and server computer |
| US5969750A (en) | 1996-09-04 | 1999-10-19 | Winbcnd Electronics Corporation | Moving picture camera with universal serial bus interface |
| CA2214743C (en) | 1996-09-20 | 2002-03-05 | Ntt Mobile Communications Network Inc. | A frame synchronization circuit and communications system |
| US5990852A (en) | 1996-10-31 | 1999-11-23 | Fujitsu Limited | Display screen duplication system and method |
| US5864546A (en) * | 1996-11-05 | 1999-01-26 | Worldspace International Network, Inc. | System for formatting broadcast data for satellite transmission and radio reception |
| US6308239B1 (en) | 1996-11-07 | 2001-10-23 | Hitachi, Ltd. | Interface switching apparatus and switching control method |
| US6078361A (en) | 1996-11-18 | 2000-06-20 | Sage, Inc | Video adapter circuit for conversion of an analog video signal to a digital display image |
| US6002709A (en) | 1996-11-21 | 1999-12-14 | Dsp Group, Inc. | Verification of PN synchronization in a direct-sequence spread-spectrum digital communications system |
| KR100211918B1 (en) | 1996-11-30 | 1999-08-02 | 김영환 | Atm cell boundary discerning apparatus |
| US5862160A (en) | 1996-12-31 | 1999-01-19 | Ericsson, Inc. | Secondary channel for communication networks |
| US5995512A (en) | 1997-01-17 | 1999-11-30 | Delco Electronics Corporation | High speed multimedia data network |
| US6064649A (en) | 1997-01-31 | 2000-05-16 | Nec Usa, Inc. | Network interface card for wireless asynchronous transfer mode networks |
| US6081513A (en) | 1997-02-10 | 2000-06-27 | At&T Corp. | Providing multimedia conferencing services over a wide area network interconnecting nonguaranteed quality of services LANs |
| EP0859326A3 (en) | 1997-02-14 | 1999-05-12 | Canon Kabushiki Kaisha | Data transmission apparatus, system and method, and image processing apparatus |
| US6359923B1 (en) | 1997-12-18 | 2002-03-19 | At&T Wireless Services, Inc. | Highly bandwidth efficient communications |
| US6584144B2 (en) | 1997-02-24 | 2003-06-24 | At&T Wireless Services, Inc. | Vertical adaptive antenna array for a discrete multitone spread spectrum communications system |
| DE19733005B4 (en) * | 1997-03-12 | 2007-06-21 | Storz Endoskop Gmbh | Device for central monitoring and / or control of at least one device |
| US6480521B1 (en) | 1997-03-26 | 2002-11-12 | Qualcomm Incorporated | Method and apparatus for transmitting high speed data in a spread spectrum communications system |
| US7143177B1 (en) | 1997-03-31 | 2006-11-28 | West Corporation | Providing a presentation on a network having a plurality of synchronized media types |
| US5963557A (en) | 1997-04-11 | 1999-10-05 | Eng; John W. | High capacity reservation multiple access network with multiple shared unidirectional paths |
| US6405111B2 (en) | 1997-05-16 | 2002-06-11 | Snap-On Technologies, Inc. | System and method for distributed computer automotive service equipment |
| JP3143079B2 (en) | 1997-05-30 | 2001-03-07 | 松下電器産業株式会社 | Dictionary index creation device and document search device |
| US5867510A (en) * | 1997-05-30 | 1999-02-02 | Motorola, Inc. | Method of and apparatus for decoding and processing messages |
| KR100550190B1 (en) * | 1997-06-03 | 2006-04-21 | 소니 가부시끼 가이샤 | A portable information process apparatus and controlling method of the same |
| US6236647B1 (en) | 1998-02-24 | 2001-05-22 | Tantivy Communications, Inc. | Dynamic frame size adjustment and selective reject on a multi-link channel to improve effective throughput and bit error rate |
| US6314479B1 (en) | 1997-08-04 | 2001-11-06 | Compaq Computer Corporation | Universal multi-pin plug and display connector for standardizing signals transmitted between a computer and a display for a PC theatre interconnectivity system |
| WO1999010719A1 (en) | 1997-08-29 | 1999-03-04 | The Regents Of The University Of California | Method and apparatus for hybrid coding of speech at 4kbps |
| US6288739B1 (en) | 1997-09-05 | 2001-09-11 | Intelect Systems Corporation | Distributed video communications system |
| US6385644B1 (en) | 1997-09-26 | 2002-05-07 | Mci Worldcom, Inc. | Multi-threaded web based user inbox for report management |
| EP1042871B1 (en) | 1997-10-14 | 2009-04-15 | Cypress Semiconductor Corporation | Digital radio-frequency transceiver |
| US6894994B1 (en) * | 1997-11-03 | 2005-05-17 | Qualcomm Incorporated | High data rate wireless packet data communications system |
| US6574211B2 (en) | 1997-11-03 | 2003-06-03 | Qualcomm Incorporated | Method and apparatus for high rate packet data transmission |
| TW408315B (en) * | 1997-11-07 | 2000-10-11 | Sharp Kk | Magnetic recording device, magnetic recording and reproducing device, and magnetic recording method |
| US6246876B1 (en) * | 1997-11-13 | 2001-06-12 | Telefonaktiebolaget L M Ericsson (Publ) | Synchronization messages for hand-off operations |
| US6091709A (en) | 1997-11-25 | 2000-07-18 | International Business Machines Corporation | Quality of service management for packet switched networks |
| US20010012293A1 (en) | 1997-12-02 | 2001-08-09 | Lars-Goran Petersen | Simultaneous transmission of voice and non-voice data on a single narrowband connection |
| US6049837A (en) | 1997-12-08 | 2000-04-11 | International Business Machines Corporation | Programmable output interface for lower level open system interconnection architecture |
| US6393008B1 (en) * | 1997-12-23 | 2002-05-21 | Nokia Movile Phones Ltd. | Control structures for contention-based packet data services in wideband CDMA |
| KR100286080B1 (en) | 1997-12-30 | 2001-04-16 | 윤종용 | A data transmitting and receiving method using data link |
| KR100251963B1 (en) | 1997-12-31 | 2000-04-15 | 윤종용 | Asynchronous transmission mode network access video phone terminal device |
| TW459184B (en) | 1998-01-23 | 2001-10-11 | Shiu Ming Wei | Multimedia message processing system |
| IL159669A0 (en) | 1998-02-20 | 2004-06-01 | Deep Video Imaging Ltd | A multi-layer display for displaying images |
| JP3004618B2 (en) | 1998-02-27 | 2000-01-31 | キヤノン株式会社 | Image input device, image input system, image transmission / reception system, image input method, and storage medium |
| JPH11249987A (en) | 1998-03-05 | 1999-09-17 | Nec Corp | Message processor, its method and storage medium storing message processing control program |
| HUP0301259A2 (en) | 1998-03-16 | 2003-08-28 | Jazio | Method and system for detecting signal transitions, and for comparation changing signals, and for emitting and receiving signals, and communication and/or signal transmitting system, and further systemband methods |
| KR100566040B1 (en) | 1998-03-19 | 2006-03-30 | 가부시끼가이샤 히다치 세이사꾸쇼 | Broadcast information delivering system |
| US6243761B1 (en) | 1998-03-26 | 2001-06-05 | Digital Equipment Corporation | Method for dynamically adjusting multimedia content of a web page by a server in accordance to network path characteristics between client and server |
| US6199169B1 (en) * | 1998-03-31 | 2001-03-06 | Compaq Computer Corporation | System and method for synchronizing time across a computer cluster |
| EP1341339A3 (en) | 1998-04-01 | 2004-01-02 | Matsushita Graphic Communication Systems, Inc. | Activation of multiple xDSL modems with implicit channel probe |
| US6101601A (en) | 1998-04-20 | 2000-08-08 | International Business Machines Corporation | Method and apparatus for hibernation within a distributed data processing system |
| US6430196B1 (en) | 1998-05-01 | 2002-08-06 | Cisco Technology, Inc. | Transmitting delay sensitive information over IP over frame relay |
| KR100413417B1 (en) | 1998-05-04 | 2004-02-14 | 엘지전자 주식회사 | Call Access Control Method for Mobile Terminal in Mobile Communication System |
| US6611503B1 (en) | 1998-05-22 | 2003-08-26 | Tandberg Telecom As | Method and apparatus for multimedia conferencing with dynamic bandwidth allocation |
| JP3792894B2 (en) | 1998-05-27 | 2006-07-05 | キヤノン株式会社 | Solid-state imaging device and solid-state imaging device |
| US6043693A (en) * | 1998-06-01 | 2000-03-28 | 3Dfx Interactive, Incorporated | Multiplexed synchronization circuits for switching frequency synthesized signals |
| US6850282B1 (en) | 1998-06-02 | 2005-02-01 | Canon Kabushiki Kaisha | Remote control of image sensing apparatus |
| JP3475081B2 (en) | 1998-06-03 | 2003-12-08 | 三洋電機株式会社 | 3D image playback method |
| US6092231A (en) | 1998-06-12 | 2000-07-18 | Qlogic Corporation | Circuit and method for rapid checking of error correction codes using cyclic redundancy check |
| JP4267092B2 (en) | 1998-07-07 | 2009-05-27 | 富士通株式会社 | Time synchronization method |
| US6510503B2 (en) | 1998-07-27 | 2003-01-21 | Mosaid Technologies Incorporated | High bandwidth memory interface |
| US6359479B1 (en) | 1998-08-04 | 2002-03-19 | Juniper Networks, Inc. | Synchronizing data transfers between two distinct clock domains |
| US6532506B1 (en) * | 1998-08-12 | 2003-03-11 | Intel Corporation | Communicating with devices over a bus and negotiating the transfer rate over the same |
| US6728263B2 (en) * | 1998-08-18 | 2004-04-27 | Microsoft Corporation | Dynamic sizing of data packets |
| EP1112642A2 (en) | 1998-09-11 | 2001-07-04 | Sharewave, Inc. | Method and apparatus for controlling communication within a computer network |
| JP2000188626A (en) | 1998-10-13 | 2000-07-04 | Texas Instr Inc <Ti> | Link and transaction layer controller with integrated microcontroller emulator |
| US7180951B2 (en) | 1998-10-30 | 2007-02-20 | Broadcom Corporation | Reduction of aggregate EMI emissions of multiple transmitters |
| US6421735B1 (en) | 1998-10-30 | 2002-07-16 | Advanced Micro Devices, Inc. | Apparatus and method for automatically selecting a network port for a home network station |
| AU1330200A (en) | 1998-10-30 | 2000-05-22 | Broadcom Corporation | Internet gigabit ethernet transmitter architecture |
| TW466410B (en) | 2000-06-16 | 2001-12-01 | Via Tech Inc | Cache device inside peripheral component interface chipset and data synchronous method to externals |
| US6545979B1 (en) * | 1998-11-27 | 2003-04-08 | Alcatel Canada Inc. | Round trip delay measurement |
| US6791379B1 (en) | 1998-12-07 | 2004-09-14 | Broadcom Corporation | Low jitter high phase resolution PLL-based timing recovery system |
| US6363439B1 (en) * | 1998-12-07 | 2002-03-26 | Compaq Computer Corporation | System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system |
| KR100315670B1 (en) | 1998-12-07 | 2001-11-29 | 윤종용 | Apparatus and method for gating transmission of cdma communication system |
| US6252526B1 (en) | 1998-12-14 | 2001-06-26 | Seiko Epson Corporation | Circuit and method for fast parallel data strobe encoding |
| US6297684B1 (en) | 1998-12-14 | 2001-10-02 | Seiko Epson Corporation | Circuit and method for switching between digital signals that have different signal rates |
| JP2000196986A (en) | 1998-12-25 | 2000-07-14 | Olympus Optical Co Ltd | Electronic image pickup device |
| US6950428B1 (en) | 1998-12-30 | 2005-09-27 | Hewlett-Packard Development Company, L.P. | System and method for configuring adaptive sets of links between routers in a system area network (SAN) |
| US6549538B1 (en) | 1998-12-31 | 2003-04-15 | Compaq Information Technologies Group, L.P. | Computer method and apparatus for managing network ports cluster-wide using a lookaside list |
| US6836469B1 (en) | 1999-01-15 | 2004-12-28 | Industrial Technology Research Institute | Medium access control protocol for a multi-channel communication system |
| JP2000216843A (en) | 1999-01-22 | 2000-08-04 | Oki Electric Ind Co Ltd | Digital demodulator |
| US6636508B1 (en) | 1999-02-12 | 2003-10-21 | Nortel Networks Limted | Network resource conservation system |
| US6493824B1 (en) | 1999-02-19 | 2002-12-10 | Compaq Information Technologies Group, L.P. | Secure system for remotely waking a computer in a power-down state |
| WO2000054177A2 (en) | 1999-03-05 | 2000-09-14 | Accenture Llp | Method and apparatus for creating an information summary |
| US6199099B1 (en) | 1999-03-05 | 2001-03-06 | Ac Properties B.V. | System, method and article of manufacture for a mobile communication network utilizing a distributed communication network |
| JP4181685B2 (en) | 1999-03-12 | 2008-11-19 | 富士通株式会社 | Power control method, electronic device, and recording medium |
| US6429867B1 (en) | 1999-03-15 | 2002-08-06 | Sun Microsystems, Inc. | System and method for generating and playback of three-dimensional movies |
| US6609167B1 (en) | 1999-03-17 | 2003-08-19 | Adaptec, Inc. | Host and device serial communication protocols and communication packet formats |
| US6636922B1 (en) | 1999-03-17 | 2003-10-21 | Adaptec, Inc. | Methods and apparatus for implementing a host side advanced serial protocol |
| FI107424B (en) | 1999-03-22 | 2001-07-31 | Nokia Mobile Phones Ltd | Method and arrangement to prepare for the transport of multimedia-related information in a cellular radio network |
| JP2000278141A (en) | 1999-03-26 | 2000-10-06 | Mitsubishi Electric Corp | Multiplexer |
| KR100350607B1 (en) | 1999-03-31 | 2002-08-28 | 삼성전자 주식회사 | Portable composite communication terminal for transmitting/receiving voice and picture data, and operating method and communication system therefor |
| US6222677B1 (en) | 1999-04-12 | 2001-04-24 | International Business Machines Corporation | Compact optical system for use in virtual display applications |
| JP2000358033A (en) | 1999-06-14 | 2000-12-26 | Canon Inc | Data communication system and data communication method |
| US6618360B1 (en) | 1999-06-15 | 2003-09-09 | Hewlett-Packard Development Company, L.P. | Method for testing data path of peripheral server devices |
| US6457090B1 (en) | 1999-06-30 | 2002-09-24 | Adaptec, Inc. | Structure and method for automatic configuration for SCSI Synchronous data transfers |
| JP2001025010A (en) * | 1999-07-09 | 2001-01-26 | Mitsubishi Electric Corp | Multi-media information communication equipment and method therefor |
| US6865609B1 (en) * | 1999-08-17 | 2005-03-08 | Sharewave, Inc. | Multimedia extensions for wireless local area network |
| US6597197B1 (en) | 1999-08-27 | 2003-07-22 | Intel Corporation | I2C repeater with voltage translation |
| KR20010019734A (en) | 1999-08-30 | 2001-03-15 | 윤종용 | System for computer training using wired and wireless communication |
| US7010607B1 (en) * | 1999-09-15 | 2006-03-07 | Hewlett-Packard Development Company, L.P. | Method for training a communication link between ports to correct for errors |
| JP3116090B1 (en) | 1999-09-17 | 2000-12-11 | 郵政省通信総合研究所長 | Communication system, transmitting device, receiving device, transmitting method, receiving method, and information recording medium |
| JP4207329B2 (en) | 1999-09-20 | 2009-01-14 | 富士通株式会社 | Frame synchronization circuit |
| US6782277B1 (en) | 1999-09-30 | 2004-08-24 | Qualcomm Incorporated | Wireless communication system with base station beam sweeping |
| US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
| US6662322B1 (en) | 1999-10-29 | 2003-12-09 | International Business Machines Corporation | Systems, methods, and computer program products for controlling the error rate in a communication device by adjusting the distance between signal constellation points |
| CA2387968A1 (en) | 1999-11-11 | 2001-05-17 | Ascom Powerline Communications Ag | Communication system, especially for indoors |
| US6438363B1 (en) | 1999-11-15 | 2002-08-20 | Lucent Technologies Inc. | Wireless modem alignment in a multi-cell environment |
| DE60005993T2 (en) | 1999-11-16 | 2004-07-29 | Broadcom Corp., Irvine | METHOD AND NETWORK SWITCH WITH DATA SERIALIZATION THROUGH SAFE, MULTI-STAGE, INTERFERENCE-FREE MULTIPLEXING |
| TW513636B (en) | 2000-06-30 | 2002-12-11 | Via Tech Inc | Bus data interface for transmitting data on PCI bus, the structure and the operating method thereof |
| US6804257B1 (en) | 1999-11-25 | 2004-10-12 | International Business Machines Corporation | System and method for framing and protecting variable-lenght packet streams |
| JP4058888B2 (en) * | 1999-11-29 | 2008-03-12 | セイコーエプソン株式会社 | RAM built-in driver and display unit and electronic device using the same |
| JP4191869B2 (en) | 1999-12-20 | 2008-12-03 | 富士フイルム株式会社 | Computer system using digital camera |
| US7383350B1 (en) | 2000-02-03 | 2008-06-03 | International Business Machines Corporation | User input based allocation of bandwidth on a data link |
| US6778493B1 (en) | 2000-02-07 | 2004-08-17 | Sharp Laboratories Of America, Inc. | Real-time media content synchronization and transmission in packet network apparatus and method |
| JP3490368B2 (en) | 2000-02-07 | 2004-01-26 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Signal output device, driver circuit, signal transmission system, and signal transmission method |
| JP2001236304A (en) | 2000-02-21 | 2001-08-31 | Mitsubishi Electric Corp | Microcomputer |
| US6477150B1 (en) | 2000-03-03 | 2002-11-05 | Qualcomm, Inc. | System and method for providing group communication services in an existing communication system |
| CA2813651C (en) | 2000-03-03 | 2014-07-08 | Qualcomm Incorporated | Method and apparatus for participating in group communication services in an existing communication system |
| JP2001282714A (en) | 2000-03-30 | 2001-10-12 | Olympus Optical Co Ltd | Multi-camera data transfer system and data transfer system |
| JP2001292146A (en) | 2000-04-07 | 2001-10-19 | Sony Corp | Electronic unit and processing method in bus initialized phase for interface device of digital serial data |
| US6882361B1 (en) * | 2000-04-19 | 2005-04-19 | Pixelworks, Inc. | Imager linked with image processing station |
| JP2001306428A (en) | 2000-04-25 | 2001-11-02 | Canon Inc | Network apparatus, network system, communication method, and recording medium |
| JP2001319745A (en) | 2000-05-08 | 2001-11-16 | Honda Tsushin Kogyo Co Ltd | Adaptor for conversion |
| JP2001320280A (en) * | 2000-05-10 | 2001-11-16 | Mitsubishi Electric Corp | Parallel/serial converting circuit |
| US6760722B1 (en) | 2000-05-16 | 2004-07-06 | International Business Machines Corporation | Computer implemented automated remote support |
| JP4292685B2 (en) | 2000-05-23 | 2009-07-08 | 日本電気株式会社 | Data transfer system, data transmission / reception system, data transmission / reception method, format conversion apparatus, format conversion method, and computer-readable recording medium recording a format conversion program |
| KR100360622B1 (en) * | 2000-06-12 | 2002-11-13 | 주식회사 문화방송 | MPEG Data frame structure and transmitting and receiving system using the same |
| US6754179B1 (en) * | 2000-06-13 | 2004-06-22 | Lsi Logic Corporation | Real time control of pause frame transmissions for improved bandwidth utilization |
| JP3415567B2 (en) | 2000-06-21 | 2003-06-09 | エヌイーシーマイクロシステム株式会社 | USB transfer control method and USB controller |
| US6714233B2 (en) | 2000-06-21 | 2004-03-30 | Seiko Epson Corporation | Mobile video telephone system |
| US6999432B2 (en) * | 2000-07-13 | 2006-02-14 | Microsoft Corporation | Channel and quality of service adaptation for multimedia over wireless networks |
| US7917602B2 (en) | 2000-08-08 | 2011-03-29 | The Directv Group, Inc. | Method and system for remote television replay control |
| US6892071B2 (en) * | 2000-08-09 | 2005-05-10 | Sk Telecom Co., Ltd. | Handover method in wireless telecommunication system supporting USTS |
| US6784941B1 (en) | 2000-08-09 | 2004-08-31 | Sunplus Technology Co., Ltd. | Digital camera with video input |
| US6725412B1 (en) | 2000-08-15 | 2004-04-20 | Dolby Laboratories Licensing Corporation | Low latency data encoder |
| JP2002062990A (en) | 2000-08-15 | 2002-02-28 | Fujitsu Media Device Kk | Interface device |
| US7138989B2 (en) | 2000-09-15 | 2006-11-21 | Silicon Graphics, Inc. | Display capable of displaying images in response to signals of a plurality of signal formats |
| US6747964B1 (en) | 2000-09-15 | 2004-06-08 | Qualcomm Incorporated | Method and apparatus for high data rate transmission in a wireless communication system |
| JP4146991B2 (en) * | 2000-09-18 | 2008-09-10 | キヤノン株式会社 | Electronic camera system, electronic camera, and control method of electronic camera system |
| US7466978B1 (en) | 2000-09-18 | 2008-12-16 | International Business Machines Corporation | Telephone network node device |
| US6760882B1 (en) | 2000-09-19 | 2004-07-06 | Intel Corporation | Mode selection for data transmission in wireless communication channels based on statistical parameters |
| US6738344B1 (en) * | 2000-09-27 | 2004-05-18 | Hewlett-Packard Development Company, L.P. | Link extenders with link alive propagation |
| US7336613B2 (en) * | 2000-10-17 | 2008-02-26 | Avaya Technology Corp. | Method and apparatus for the assessment and optimization of network traffic |
| US6690655B1 (en) | 2000-10-19 | 2004-02-10 | Motorola, Inc. | Low-powered communication system and method of operation |
| US7869067B2 (en) | 2000-10-20 | 2011-01-11 | Visioneer, Inc. | Combination scanner and image data reader system including image management and software |
| US7278069B2 (en) | 2000-10-31 | 2007-10-02 | Igor Anatolievich Abrosimov | Data transmission apparatus for high-speed transmission of digital data and method for automatic skew calibration |
| US8996698B1 (en) | 2000-11-03 | 2015-03-31 | Truphone Limited | Cooperative network for mobile internet access |
| CN1214553C (en) | 2000-11-17 | 2005-08-10 | 三星电子株式会社 | Apparatus and method for measuring propagation delay in an NB-Tdd CDMA mobile communication system |
| US7464877B2 (en) | 2003-11-13 | 2008-12-16 | Metrologic Instruments, Inc. | Digital imaging-based bar code symbol reading system employing image cropping pattern generator and automatic cropped image processor |
| FI115802B (en) | 2000-12-04 | 2005-07-15 | Nokia Corp | Refresh the photo frames on the memory display |
| GB2399264B (en) * | 2000-12-06 | 2005-02-09 | Fujitsu Ltd | Processing high-speed digital signals |
| US6973039B2 (en) * | 2000-12-08 | 2005-12-06 | Bbnt Solutions Llc | Mechanism for performing energy-based routing in wireless networks |
| MXPA03005310A (en) | 2000-12-15 | 2004-03-26 | Qualcomm Inc | Generating and implementing a communication protocol and interface for high data rate signal transfer. |
| US6760772B2 (en) | 2000-12-15 | 2004-07-06 | Qualcomm, Inc. | Generating and implementing a communication protocol and interface for high data rate signal transfer |
| JP2002208844A (en) | 2001-01-12 | 2002-07-26 | Nec Eng Ltd | Glitch elimination circuit |
| US6947436B2 (en) | 2001-02-01 | 2005-09-20 | Motorola, Inc. | Method for optimizing forward link data transmission rates in spread-spectrum communications systems |
| US7301968B2 (en) | 2001-03-02 | 2007-11-27 | Pmc-Sierra Israel Ltd. | Communication protocol for passive optical network topologies |
| KR20020071226A (en) | 2001-03-05 | 2002-09-12 | 삼성전자 주식회사 | Apparatus and method for controlling transmission of reverse link in mobile communication system |
| JP4106226B2 (en) | 2001-03-26 | 2008-06-25 | 松下電器産業株式会社 | Power control device |
| CN1165141C (en) | 2001-03-27 | 2004-09-01 | 华为技术有限公司 | Method for interface drive repeating procedure of router |
| JP2002300299A (en) | 2001-03-29 | 2002-10-11 | Shunichi Toyoda | Education system for information terminal equipment utilizing memory of portable telephone |
| JP3497834B2 (en) | 2001-03-30 | 2004-02-16 | 株式会社東芝 | Route repeater, USB communication system, USB communication control method |
| CN1159935C (en) | 2001-03-30 | 2004-07-28 | 华为技术有限公司 | Method and device for raising cellular mobile station positioning accuracy in urban environment |
| JP2002359774A (en) | 2001-03-30 | 2002-12-13 | Fuji Photo Film Co Ltd | Electronic camera |
| US20020188754A1 (en) | 2001-04-27 | 2002-12-12 | Foster Michael S. | Method and system for domain addressing in a communications network |
| US6889056B2 (en) | 2001-04-30 | 2005-05-03 | Ntt Docomo, Inc. | Transmission control scheme |
| JP3884322B2 (en) | 2001-05-16 | 2007-02-21 | 株式会社リコー | Network interface |
| US7392541B2 (en) | 2001-05-17 | 2008-06-24 | Vir2Us, Inc. | Computer system architecture and method providing operating-system independent virus-, hacker-, and cyber-terror-immune processing environments |
| AU2002305780A1 (en) | 2001-05-29 | 2002-12-09 | Transchip, Inc. | Patent application cmos imager for cellular applications and methods of using such |
| JP2002351689A (en) | 2001-05-30 | 2002-12-06 | Nec Corp | Data transfer system |
| US7191281B2 (en) * | 2001-06-13 | 2007-03-13 | Intel Corporation | Mobile computer system having a navigation mode to optimize system performance and power management for mobile applications |
| US7165112B2 (en) * | 2001-06-22 | 2007-01-16 | Motorola, Inc. | Method and apparatus for transmitting data in a communication system |
| JP2003006143A (en) | 2001-06-22 | 2003-01-10 | Nec Corp | System, device and method of sharing bus |
| US6745364B2 (en) * | 2001-06-28 | 2004-06-01 | Microsoft Corporation | Negotiated/dynamic error correction for streamed media |
| JP2003046595A (en) | 2001-07-06 | 2003-02-14 | Texas Instruments Inc | Method and apparatus for data communication |
| US7051218B1 (en) * | 2001-07-18 | 2006-05-23 | Advanced Micro Devices, Inc. | Message based power management |
| WO2003013080A1 (en) | 2001-07-31 | 2003-02-13 | Comverse Ltd. | Email protocol for a mobile environment and gateway using same |
| US7184408B2 (en) * | 2001-07-31 | 2007-02-27 | Denton I Claude | Method and apparatus for programmable generation of traffic streams |
| JP2003044184A (en) | 2001-08-01 | 2003-02-14 | Canon Inc | Data processor and method for controlling power |
| GB2415314B (en) * | 2001-08-08 | 2006-05-03 | Adder Tech Ltd | Video switch |
| JP4733877B2 (en) | 2001-08-15 | 2011-07-27 | 富士通セミコンダクター株式会社 | Semiconductor device |
| JP2003069544A (en) | 2001-08-23 | 2003-03-07 | Hitachi Kokusai Electric Inc | Method and device for controlling communication |
| JP4322451B2 (en) | 2001-09-05 | 2009-09-02 | 日本電気株式会社 | Data transfer method between DSP memories or between DSP memory and CPU memory (DPRAM) |
| US8812706B1 (en) * | 2001-09-06 | 2014-08-19 | Qualcomm Incorporated | Method and apparatus for compensating for mismatched delays in signals of a mobile display interface (MDDI) system |
| CN1575448A (en) | 2001-09-06 | 2005-02-02 | 高通股份有限公司 | Generating and implementing a communication protocol and interface for high data rate signal transfer |
| DE10145722A1 (en) | 2001-09-17 | 2003-04-24 | Infineon Technologies Ag | Concept for secure data communication between electronic components |
| US20030061431A1 (en) * | 2001-09-21 | 2003-03-27 | Intel Corporation | Multiple channel interface for communications between devices |
| KR100408299B1 (en) | 2001-09-29 | 2003-12-01 | 삼성전자주식회사 | Apparatus and method for detecting display mode |
| JP3633538B2 (en) | 2001-10-02 | 2005-03-30 | 日本電気株式会社 | Congestion control system |
| US7570668B2 (en) | 2001-10-03 | 2009-08-04 | Nokia Corporation | Data synchronization |
| KR100408525B1 (en) | 2001-10-31 | 2003-12-06 | 삼성전자주식회사 | System and method of network adaptive real- time multimedia streaming |
| US20030125040A1 (en) | 2001-11-06 | 2003-07-03 | Walton Jay R. | Multiple-access multiple-input multiple-output (MIMO) communication system |
| US7126945B2 (en) * | 2001-11-07 | 2006-10-24 | Symbol Technologies, Inc. | Power saving function for wireless LANS: methods, system and program products |
| US6990549B2 (en) * | 2001-11-09 | 2006-01-24 | Texas Instruments Incorporated | Low pin count (LPC) I/O bridge |
| US7536598B2 (en) | 2001-11-19 | 2009-05-19 | Vir2Us, Inc. | Computer system capable of supporting a plurality of independent computing environments |
| US6891545B2 (en) | 2001-11-20 | 2005-05-10 | Koninklijke Philips Electronics N.V. | Color burst queue for a shared memory controller in a color sequential display system |
| GB2382502B (en) | 2001-11-23 | 2005-10-19 | Actix Ltd | Network testing systems |
| JP2003167680A (en) | 2001-11-30 | 2003-06-13 | Hitachi Ltd | Disk device |
| US7486693B2 (en) | 2001-12-14 | 2009-02-03 | General Electric Company | Time slot protocol |
| US6993393B2 (en) | 2001-12-19 | 2006-01-31 | Cardiac Pacemakers, Inc. | Telemetry duty cycle management system for an implantable medical device |
| JP2003198550A (en) | 2001-12-25 | 2003-07-11 | Matsushita Electric Ind Co Ltd | Communication device and communication method |
| KR100428767B1 (en) | 2002-01-11 | 2004-04-28 | 삼성전자주식회사 | method and recorded media for setting the subscriber routing using traffic information |
| US20030144006A1 (en) | 2002-01-25 | 2003-07-31 | Mikael Johansson | Methods, systems, and computer program products for determining the location of a mobile terminal based on delays in receiving data packets from transmitters having known locations |
| US20050120208A1 (en) | 2002-01-25 | 2005-06-02 | Albert Dobson Robert W. | Data transmission systems |
| US6690201B1 (en) * | 2002-01-28 | 2004-02-10 | Xilinx, Inc. | Method and apparatus for locating data transition regions |
| US6797891B1 (en) | 2002-03-18 | 2004-09-28 | Applied Micro Circuits Corporation | Flexible interconnect cable with high frequency electrical transmission line |
| US7145411B1 (en) | 2002-03-18 | 2006-12-05 | Applied Micro Circuits Corporation | Flexible differential interconnect cable with isolated high frequency electrical transmission line |
| US7336139B2 (en) | 2002-03-18 | 2008-02-26 | Applied Micro Circuits Corporation | Flexible interconnect cable with grounded coplanar waveguide |
| US6867668B1 (en) | 2002-03-18 | 2005-03-15 | Applied Micro Circuits Corporation | High frequency signal transmission from the surface of a circuit substrate to a flexible interconnect cable |
| US20030185220A1 (en) | 2002-03-27 | 2003-10-02 | Moshe Valenci | Dynamically loading parsing capabilities |
| US7310535B1 (en) | 2002-03-29 | 2007-12-18 | Good Technology, Inc. | Apparatus and method for reducing power consumption in a wireless device |
| US7425986B2 (en) | 2002-03-29 | 2008-09-16 | Canon Kabushiki Kaisha | Conversion apparatus for image data delivery |
| US7430001B2 (en) | 2002-04-12 | 2008-09-30 | Canon Kabushiki Kaisha | Image sensing system, communication apparatus and image sensing apparatus having remote control function, and their control method |
| TWI235917B (en) | 2002-04-15 | 2005-07-11 | Via Tech Inc | High speed data transmitter and transmission method thereof |
| US7158539B2 (en) | 2002-04-16 | 2007-01-02 | Microsoft Corporation | Error resilient windows media audio coding |
| US7599689B2 (en) | 2002-04-22 | 2009-10-06 | Nokia Corporation | System and method for bookmarking radio stations and associated internet addresses |
| JP4029390B2 (en) | 2002-04-23 | 2008-01-09 | ソニー株式会社 | Information processing system, information processing apparatus and method, program storage medium, and program |
| US7284181B1 (en) | 2002-04-24 | 2007-10-16 | Juniper Networks, Inc. | Systems and methods for implementing end-to-end checksum |
| US7206516B2 (en) | 2002-04-30 | 2007-04-17 | Pivotal Decisions Llc | Apparatus and method for measuring the dispersion of a fiber span |
| US7574113B2 (en) | 2002-05-06 | 2009-08-11 | Sony Corporation | Video and audio data recording apparatus, video and audio data recording method, video and audio data reproducing apparatus, and video and audio data reproducing method |
| US20050091593A1 (en) | 2002-05-10 | 2005-04-28 | General Electric Company | Method and system for coordinated transfer of control of a remote controlled locomotive |
| US6886067B2 (en) | 2002-05-23 | 2005-04-26 | Seiko Epson Corporation | 32 Bit generic asynchronous bus interface using read/write strobe byte enables |
| US7036066B2 (en) * | 2002-05-24 | 2006-04-25 | Sun Microsystems, Inc. | Error detection using data block mapping |
| US7269153B1 (en) | 2002-05-24 | 2007-09-11 | Conexant Systems, Inc. | Method for minimizing time critical transmit processing for a personal computer implementation of a wireless local area network adapter |
| US7543326B2 (en) | 2002-06-10 | 2009-06-02 | Microsoft Corporation | Dynamic rate control |
| JP2003098583A (en) | 2002-06-10 | 2003-04-03 | Nikon Corp | Camera using rewritable memory |
| JP2004021613A (en) | 2002-06-17 | 2004-01-22 | Seiko Epson Corp | Data transfer controller, electronic apparatus, and data transfer control method |
| EP1376945B1 (en) | 2002-06-18 | 2006-06-07 | Matsushita Electric Industrial Co., Ltd. | Receiver-based RTT measurement in TCP |
| KR100469427B1 (en) | 2002-06-24 | 2005-02-02 | 엘지전자 주식회사 | Video reproducing method for mobile communication system |
| US7486696B2 (en) | 2002-06-25 | 2009-02-03 | Avaya, Inc. | System and method for providing bandwidth management for VPNs |
| JP4175838B2 (en) | 2002-07-09 | 2008-11-05 | 三菱電機株式会社 | Information processing apparatus with standby mode, standby mode start method and standby mode cancel method |
| DE10234991B4 (en) * | 2002-07-31 | 2008-07-31 | Advanced Micro Devices, Inc., Sunnyvale | Host controller diagnostics for a serial bus |
| US7403511B2 (en) | 2002-08-02 | 2008-07-22 | Texas Instruments Incorporated | Low power packet detector for low power WLAN devices |
| US6611221B1 (en) | 2002-08-26 | 2003-08-26 | Texas Instruments Incorporated | Multi-bit sigma-delta modulator employing dynamic element matching using adaptively randomized data-weighted averaging |
| MXPA05002511A (en) * | 2002-09-05 | 2005-08-16 | Agency Science Tech & Res | A method and an apparatus for controlling the rate of a video sequence; a video encoding device. |
| WO2004025365A1 (en) | 2002-09-13 | 2004-03-25 | Digimarc Id Systems, Llc | Enhanced shadow reduction system and related techniques for digital image capture |
| US7257087B2 (en) | 2002-10-04 | 2007-08-14 | Agilent Technologies, Inc. | System and method to calculate round trip delay for real time protocol packet streams |
| CN1266976C (en) | 2002-10-15 | 2006-07-26 | 华为技术有限公司 | Mobile station positioning method and its direct broadcasting station |
| US20040082383A1 (en) | 2002-10-24 | 2004-04-29 | Motorola, Inc | Methodology and wireless device for interactive gaming |
| JP4028356B2 (en) | 2002-10-31 | 2007-12-26 | 京セラ株式会社 | COMMUNICATION SYSTEM, RADIO COMMUNICATION TERMINAL, DATA DISTRIBUTION DEVICE, AND COMMUNICATION METHOD |
| GB0226014D0 (en) | 2002-11-08 | 2002-12-18 | Nokia Corp | Camera-LSI and information device |
| US7336667B2 (en) * | 2002-11-21 | 2008-02-26 | International Business Machines Corporation | Apparatus, method and program product to generate and use CRC in communications network |
| US7327735B2 (en) * | 2002-11-27 | 2008-02-05 | Alcatel Canada Inc. | System and method for detecting lost messages transmitted between modules in a communication device |
| JP3642332B2 (en) | 2002-12-20 | 2005-04-27 | 松下電器産業株式会社 | Folding mobile phone device |
| US7191349B2 (en) | 2002-12-26 | 2007-03-13 | Intel Corporation | Mechanism for processor power state aware distribution of lowest priority interrupt |
| US6765506B1 (en) | 2003-01-06 | 2004-07-20 | Via Technologies Inc. | Scrambler, de-scrambler, and related method |
| GB2397709B (en) | 2003-01-27 | 2005-12-28 | Evangelos Arkas | Period-to-digital converter |
| US7047475B2 (en) * | 2003-02-04 | 2006-05-16 | Hewlett-Packard Development Company, L.P. | CRC encoding scheme for conveying status information |
| JP4119764B2 (en) | 2003-02-13 | 2008-07-16 | 京セラ株式会社 | Mobile device with camera |
| US20040176065A1 (en) | 2003-02-20 | 2004-09-09 | Bo Liu | Low power operation in a personal area network communication system |
| US7787886B2 (en) * | 2003-02-24 | 2010-08-31 | Invisitrack, Inc. | System and method for locating a target using RFID |
| US6944136B2 (en) | 2003-02-28 | 2005-09-13 | On-Demand Technologies, Inc. | Two-way audio/video conferencing system |
| US20040184450A1 (en) | 2003-03-19 | 2004-09-23 | Abdu H. Omran | Method and system for transport and routing of packets over frame-based networks |
| JP4112414B2 (en) | 2003-03-28 | 2008-07-02 | 京セラ株式会社 | Mobile terminal device |
| US7260087B2 (en) | 2003-04-02 | 2007-08-21 | Cellco Partnership | Implementation methodology for client initiated parameter negotiation for PTT/VoIP type services |
| JP2004309623A (en) | 2003-04-03 | 2004-11-04 | Konica Minolta Opto Inc | Imaging apparatus, mobile terminal and imaging apparatus manufacturing method |
| JP4288994B2 (en) * | 2003-04-10 | 2009-07-01 | 株式会社日立製作所 | Terminal device, distribution server, video data receiving method, and video data transmitting method |
| US20040221315A1 (en) | 2003-05-01 | 2004-11-04 | Genesis Microchip Inc. | Video interface arranged to provide pixel data independent of a link character clock |
| US6895410B2 (en) * | 2003-05-02 | 2005-05-17 | Nokia Corporation | Method and apparatus for providing a multimedia data stream |
| US7477604B2 (en) | 2003-05-14 | 2009-01-13 | Ntt Docomo, Inc. | Packet communications system |
| WO2004107678A2 (en) | 2003-05-28 | 2004-12-09 | Artimi Ltd | Ultra-wideband network, device, device controller, method and data packet for establishing a mesh network and forwarding packets on another channel |
| US7110420B2 (en) | 2003-05-30 | 2006-09-19 | North Carolina State University | Integrated circuit devices having on-chip adaptive bandwidth buses and related methods |
| CN103220282B (en) | 2003-06-02 | 2016-05-25 | 高通股份有限公司 | Generate and implement one for more signal protocol and the interface of High Data Rate |
| JP4278439B2 (en) | 2003-06-02 | 2009-06-17 | パイオニア株式会社 | Information communication apparatus, system thereof, method thereof, program thereof, and recording medium recording the program |
| US6975145B1 (en) | 2003-06-02 | 2005-12-13 | Xilinx, Inc. | Glitchless dynamic multiplexer with synchronous and asynchronous controls |
| US20040260823A1 (en) | 2003-06-17 | 2004-12-23 | General Instrument Corporation | Simultaneously transporting multiple MPEG-2 transport streams |
| JP3834819B2 (en) * | 2003-07-17 | 2006-10-18 | 船井電機株式会社 | projector |
| KR100538226B1 (en) | 2003-07-18 | 2005-12-21 | 삼성전자주식회사 | Analog to digital converting device for processing plural analog input signal by high speed and display apparatus using the same |
| US7526350B2 (en) | 2003-08-06 | 2009-04-28 | Creative Technology Ltd | Method and device to process digital media streams |
| EP2363989B1 (en) | 2003-08-13 | 2018-09-19 | Qualcomm Incorporated | A signal interface for higher data rates |
| RU2369033C2 (en) * | 2003-09-10 | 2009-09-27 | Квэлкомм Инкорпорейтед | High-speed data transmission interface |
| US7015838B1 (en) * | 2003-09-11 | 2006-03-21 | Xilinx, Inc. | Programmable serializing data path |
| KR20050028396A (en) | 2003-09-17 | 2005-03-23 | 삼성전자주식회사 | Method of recording data using multi-session, and the information storage medium therefor |
| ATE387824T1 (en) * | 2003-10-08 | 2008-03-15 | Research In Motion Ltd | METHOD AND DEVICE FOR DYNAMIC PACKET TRANSMISSION IN CDMA2000 NETWORKS |
| CN1894931A (en) | 2003-10-15 | 2007-01-10 | 高通股份有限公司 | High data rate interface |
| RU2331160C2 (en) | 2003-10-29 | 2008-08-10 | Квэлкомм Инкорпорейтед | Interface with high speed of data transmission |
| US8606946B2 (en) | 2003-11-12 | 2013-12-10 | Qualcomm Incorporated | Method, system and computer program for driving a data signal in data interface communication data link |
| US7219294B2 (en) * | 2003-11-14 | 2007-05-15 | Intel Corporation | Early CRC delivery for partial frame |
| US7447953B2 (en) | 2003-11-14 | 2008-11-04 | Intel Corporation | Lane testing with variable mapping |
| US7143207B2 (en) | 2003-11-14 | 2006-11-28 | Intel Corporation | Data accumulation between data path having redrive circuit and memory device |
| CA2546971A1 (en) | 2003-11-25 | 2005-06-09 | Qualcomm Incorporated | High data rate interface with improved link synchronization |
| CA2731363C (en) | 2003-12-08 | 2013-10-08 | Qualcomm Incorporated | High data rate interface with improved link synchronization |
| US7451362B2 (en) | 2003-12-12 | 2008-11-11 | Broadcom Corporation | Method and system for onboard bit error rate (BER) estimation in a port bypass controller |
| US7340548B2 (en) | 2003-12-17 | 2008-03-04 | Microsoft Corporation | On-chip bus |
| US20050163085A1 (en) | 2003-12-24 | 2005-07-28 | International Business Machines Corporation | System and method for autonomic wireless presence ping |
| US7317754B1 (en) | 2004-01-12 | 2008-01-08 | Verizon Services Corp. | Rate agile rate-adaptive digital subscriber line |
| KR20060128982A (en) | 2004-01-28 | 2006-12-14 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | Displaying on a matrix display |
| US7158536B2 (en) * | 2004-01-28 | 2007-01-02 | Rambus Inc. | Adaptive-allocation of I/O bandwidth using a configurable interconnect topology |
| US7868890B2 (en) | 2004-02-24 | 2011-01-11 | Qualcomm Incorporated | Display processor for a wireless device |
| CN101827103B (en) | 2004-03-10 | 2012-07-04 | 高通股份有限公司 | High data rate interface apparatus and method |
| KR101245962B1 (en) | 2004-03-17 | 2013-03-21 | 퀄컴 인코포레이티드 | High data rate interface apparatus and method |
| WO2005096594A1 (en) | 2004-03-24 | 2005-10-13 | Qualcomm Incorporated | High data rate interface apparatus and method |
| DE102004014973B3 (en) | 2004-03-26 | 2005-11-03 | Infineon Technologies Ag | Parallel-serial converter |
| US20050248685A1 (en) | 2004-04-21 | 2005-11-10 | Samsung Electronics Co., Ltd. | Multidata processing device and method in a wireless terminal |
| US20050265333A1 (en) | 2004-06-01 | 2005-12-01 | Texas Instruments Incorporated | Method for enabling efficient multicast transmission in a packet-based network |
| US7088294B2 (en) | 2004-06-02 | 2006-08-08 | Research In Motion Limited | Mobile wireless communications device comprising a top-mounted auxiliary input/output device and a bottom-mounted antenna |
| CA2569106C (en) * | 2004-06-04 | 2013-05-21 | Qualcomm Incorporated | High data rate interface apparatus and method |
| US8650304B2 (en) * | 2004-06-04 | 2014-02-11 | Qualcomm Incorporated | Determining a pre skew and post skew calibration data rate in a mobile display digital interface (MDDI) communication system |
| US20060034301A1 (en) | 2004-06-04 | 2006-02-16 | Anderson Jon J | High data rate interface apparatus and method |
| US7383399B2 (en) * | 2004-06-30 | 2008-06-03 | Intel Corporation | Method and apparatus for memory compression |
| US7095435B1 (en) | 2004-07-21 | 2006-08-22 | Hartman Richard L | Programmable multifunction electronic camera |
| EP1799643B1 (en) | 2004-07-22 | 2010-09-22 | UCB Pharma, S.A. | Indolone derivatives, processes for preparing them and their uses |
| CN101041989A (en) | 2004-08-05 | 2007-09-26 | 邱则有 | Reinforced bar concrete solid load-carrying structural storied building cover |
| KR100604323B1 (en) | 2004-08-28 | 2006-07-24 | 삼성테크윈 주식회사 | Embedded camera apparatus and mobile phone including the same |
| KR100624311B1 (en) | 2004-08-30 | 2006-09-19 | 삼성에스디아이 주식회사 | Method for controlling frame memory and display device using the same |
| US7161846B2 (en) * | 2004-11-16 | 2007-01-09 | Seiko Epson Corporation | Dual-edge triggered multiplexer flip-flop and method |
| CN101449255B (en) | 2004-11-24 | 2011-08-31 | 高通股份有限公司 | Methods and systems for updating a buffer |
| US8692838B2 (en) | 2004-11-24 | 2014-04-08 | Qualcomm Incorporated | Methods and systems for updating a buffer |
| US8873584B2 (en) | 2004-11-24 | 2014-10-28 | Qualcomm Incorporated | Digital data interface device |
| US8667363B2 (en) | 2004-11-24 | 2014-03-04 | Qualcomm Incorporated | Systems and methods for implementing cyclic redundancy checks |
| WO2006058173A2 (en) | 2004-11-24 | 2006-06-01 | Qualcomm Incorporated | Digital data interface device message format |
| US20060161691A1 (en) | 2004-11-24 | 2006-07-20 | Behnam Katibian | Methods and systems for synchronous execution of commands across a communication link |
| US8699330B2 (en) * | 2004-11-24 | 2014-04-15 | Qualcomm Incorporated | Systems and methods for digital data transmission rate control |
| US7315265B2 (en) * | 2004-11-24 | 2008-01-01 | Qualcomm Incorporated | Double data rate serial encoder |
| US8539119B2 (en) | 2004-11-24 | 2013-09-17 | Qualcomm Incorporated | Methods and apparatus for exchanging messages having a digital data interface device message format |
| KR100672987B1 (en) | 2004-12-20 | 2007-01-24 | 삼성전자주식회사 | High speed analog envelope detector |
| JP2006211394A (en) * | 2005-01-28 | 2006-08-10 | Toshiba Corp | Foldable portable terminal device |
| US7412642B2 (en) | 2005-03-09 | 2008-08-12 | Sun Microsystems, Inc. | System and method for tolerating communication lane failures |
| JP4428272B2 (en) | 2005-03-28 | 2010-03-10 | セイコーエプソン株式会社 | Display driver and electronic device |
| US7605837B2 (en) | 2005-06-02 | 2009-10-20 | Lao Chan Yuen | Display system and method |
| JP2007012937A (en) | 2005-06-30 | 2007-01-18 | Seiko Epson Corp | Display driver |
| JP4756950B2 (en) | 2005-08-08 | 2011-08-24 | キヤノン株式会社 | Imaging apparatus and control method thereof |
| US7302510B2 (en) * | 2005-09-29 | 2007-11-27 | International Business Machines Corporation | Fair hierarchical arbiter |
| US8730069B2 (en) | 2005-11-23 | 2014-05-20 | Qualcomm Incorporated | Double data rate serial encoder |
| US8692839B2 (en) | 2005-11-23 | 2014-04-08 | Qualcomm Incorporated | Methods and systems for updating a buffer |
| US7893990B1 (en) | 2006-07-31 | 2011-02-22 | Cisco Technology, Inc. | Digital video camera with retractable data connector and resident software application |
| JP4250648B2 (en) | 2006-09-21 | 2009-04-08 | 株式会社東芝 | Information processing device |
| US7912503B2 (en) * | 2007-07-16 | 2011-03-22 | Microsoft Corporation | Smart interface system for mobile communications devices |
| JP2009284281A (en) | 2008-05-23 | 2009-12-03 | Nec Electronics Corp | Wireless communication device, and method for displaying wireless communication state |
| KR200469360Y1 (en) | 2008-12-26 | 2013-10-11 | 대성전기공업 주식회사 | Control Switch for Seat Temperature |
-
2006
- 2006-08-08 US US11/463,129 patent/US8723705B2/en active Active
-
2007
- 2007-08-02 RU RU2009108263/09A patent/RU2009108263A/en unknown
- 2007-08-02 EP EP07813729.6A patent/EP2055008B1/en active Active
- 2007-08-02 ES ES12189620.3T patent/ES2460723T3/en active Active
- 2007-08-02 ES ES07813729.6T patent/ES2440491T3/en active Active
- 2007-08-02 CN CN2007800293195A patent/CN101502000B/en active Active
- 2007-08-02 JP JP2009523912A patent/JP5038418B2/en not_active Expired - Fee Related
- 2007-08-02 KR KR1020097004894A patent/KR101096932B1/en active IP Right Grant
- 2007-08-02 WO PCT/US2007/075127 patent/WO2008021749A1/en active Application Filing
- 2007-08-02 BR BRPI0714865-8A patent/BRPI0714865B1/en active IP Right Grant
- 2007-08-02 CA CA2658561A patent/CA2658561C/en not_active Expired - Fee Related
- 2007-08-02 EP EP12189620.3A patent/EP2552026B1/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| ES2440491T3 (en) | 2014-01-29 |
| KR20090051083A (en) | 2009-05-20 |
| CN101502000B (en) | 2011-10-19 |
| RU2009108263A (en) | 2010-09-20 |
| CN101502000A (en) | 2009-08-05 |
| EP2552026A1 (en) | 2013-01-30 |
| KR101096932B1 (en) | 2011-12-22 |
| JP5038418B2 (en) | 2012-10-03 |
| EP2055008B1 (en) | 2013-11-20 |
| US8723705B2 (en) | 2014-05-13 |
| EP2552026B1 (en) | 2014-03-26 |
| US20080036631A1 (en) | 2008-02-14 |
| BRPI0714865B1 (en) | 2023-05-09 |
| WO2008021749A1 (en) | 2008-02-21 |
| CA2658561A1 (en) | 2008-02-21 |
| BRPI0714865A2 (en) | 2013-05-28 |
| ES2460723T3 (en) | 2014-05-14 |
| JP2010500822A (en) | 2010-01-07 |
| EP2055008A1 (en) | 2009-05-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2658561C (en) | Low output skew double data rate serial encoder | |
| US8730069B2 (en) | Double data rate serial encoder | |
| EP1815626B1 (en) | Double data rate serial encoder | |
| US7315265B2 (en) | Double data rate serial encoder | |
| US8619762B2 (en) | Low power deserializer and demultiplexing method | |
| CA2676079C (en) | Three phase and polarity encoded serial interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20220301 |
|
| MKLA | Lapsed |
Effective date: 20200831 |