CN101425810B - Pulse ultra wideband receiver - Google Patents
Pulse ultra wideband receiver Download PDFInfo
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- CN101425810B CN101425810B CN200810218233A CN200810218233A CN101425810B CN 101425810 B CN101425810 B CN 101425810B CN 200810218233 A CN200810218233 A CN 200810218233A CN 200810218233 A CN200810218233 A CN 200810218233A CN 101425810 B CN101425810 B CN 101425810B
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Abstract
The invention discloses a pulse super-broadband receiver which comprises a controllable gain amplifier and a triggering receiver in mutual connection, wherein the controllable gain amplifier amplifies a received RF signal and outputs the RF signal to the triggering receiver, and the triggering receiver judges whether the energy of the amplified RF signal excesses the preset value, if the energy of the amplified RF signal excesses the preset value, asynchronous triggering is carried out to obtain high electric level, or else, low electric level is obtained. The pulse super-broadband receiver uses a simple digital logic circuit for receiving the super-broadband pulse, avoids the limitations of high power consumption, complex circuits, difficult integration, and the like of the traditional synchronous sampling receiving method in receiving super-broadband signals, has the advantages of simple circuits, easy integration and low power consumption, and is particularly suitable for the super-broadband pulse communication. The invention can correctly receive the signal and greatly reduce the power consumption and the complexity of the receiving circuit, and is helpful for chip realization.
Description
Technical field
The present invention relates to radio communication and IC design field, be specifically related to a kind of pulse ultra wideband receiver.
Background technology
Ultra broadband (ultra-wideband, UWB) technology has attracted people's research interest in recent years with its special advantages, and it has application promise in clinical practice in the wireless data transmission field.
At present, the signal acceptance method of UWB transmission system research is main still from communication theory, and is main with the method that follows the traditional narrow transmission system.Famous Shannon (Shannon) communication theory provided additive white Gaussian noise (additive white Gauss noise, AWGN) under the channel, the relation between rate of information throughput C and the resource overhead (signal energy Eb and occupied frequency bandwidth W).People are when the research signal acceptance method; Always go to approach the Shannon limit as far as possible; The correlative study of matched filtering provides; In linear method of reseptance, cross-correlation (cross-correlate) method can make the relation between signal energy expense Eb, band efficiency W/Rb and the error performance Pb reach optimization.The method need be obtained the full detail (amplitude and timing that comprise signal) that receives signal, generally relies on the synchronized sampling circuit to realize, therefore is also referred to as synchronized sampling cross-correlation (or matched filtering) method.The application of this synchronized sampling cross-correlation method of reseptance in the narrow band transmission system is relatively ripe, and existing UWB transmission system generally also all follows this method of reseptance.
But, this limitation that it is arranged based on the synchronized sampling method of reseptance of communication theory.
On the one hand, the Shannon theory has its limitation.A complete data transmission system; Its energy expense had both comprised the signal energy Eb of the information of carrying; The energy consumption Ec that also comprises signal processing; And the Shannon communication theory has only been considered the signal energy Eb of the information of carrying when analyzing system performance, does not consider the energy expense Ec in the processing signals process.In the actual transmissions system, when the relation between Eb and other parameter reached optimal situation, the cost Ec of signal processing circuit may be bigger, may not be optimized thereby the energy expense of whole system is power consumption Eb+Ec.
Correspondingly, the synchronized sampling method of reseptance also has its limitation.This is a kind of pursuit signal energy expense and the optimized method of reseptance of band efficiency, and the UWB transmission system with have narrowband systems now and share frequency band, so band efficiency no longer is one of optimization aim.But the UWB transmission system is in order to keep the compatibility with narrowband systems; Must use low power spectral density, wide band narrow pulse signal; Its bandwidth W can not reduce as narrowband systems; Must keep very high sample rate f s=2W when therefore receiving the UWB signal with synchronous sampling method, according to Circuit theory, this will cause very high power consumption P.And that the data rate Rb of more actual transmissions system does not reach the UWB sample rate (as more than the 1GHz) is high, and this just causes the required receiver upset number of times of every transmission 1bit data very high, makes the bit energy consumption Ec of unit of circuit worsen.It is thus clear that synchronized sampling receives and not too to be suitable for the UWB transmission system, particularly Rb＜＜the low-speed applications situation of fs (as be lower than 100Mb/s data rate).
Summary of the invention
Technical problem to be solved by this invention is exactly in order to overcome above deficiency, to have proposed the little pulse ultra wideband receiver of a kind of power consumption.
Technical problem of the present invention solves through following technical scheme:
A kind of pulse ultra wideband receiver; Comprise interconnective controllable gain amplifier and trigger receiver; Said controllable gain amplifier amplifies the radiofrequency signal that receives and exports to the triggering receiver; Said triggering receiver judges whether the energy of the radiofrequency signal after amplifying surpasses preset value, if just carry out asynchronous triggering, obtain high level, otherwise obtains low level.
Said triggering receiver comprises impulsive synchronization module, phase deflection correction module and phase-locked loop; Said impulsive synchronization module is coupling between controllable gain amplifier and the phase deflection correction module; Said phase-locked loop is exported first clock to impulsive synchronization module, phase deflection correction module; Said impulsive synchronization device obtains synchronizing signal and exports to the phase deflection correction module under first clock radiofrequency signal after amplifying being carried out impulsive synchronization, and said phase deflection correction module is carried out the correction of phase deviation to synchronizing signal under first clock.
Said pulse ultra wideband receiver also comprises data statistics module; Said data statistics module is coupling between phase deflection correction module and the controllable gain amplifier; Said data statistics module also receives first clock of phase-locked loop output; Said data statistics module statistics compares the corresponding gain control signal of back generation at the number of certain hour high level of phase deflection correction module output in the cycle and with fiducial value, exports the gain control input of controllable gain amplifier to.
Said impulsive synchronization module comprises PMOS pipe, NMOS pipe, first electric capacity, delayer, first d type flip flop, second d type flip flop; The source electrode of said PMOS pipe connects power supply; Grid links to each other with the output of said controllable gain amplifier; The drain electrode of the drain electrode of said PMOS pipe and NMOS pipe links to each other after first capacity earth, the source ground that said NMOS manages; The serial connection point of said PMOS pipe of the input termination of said delayer and NMOS pipe, the set end of said first d type flip flop of output termination, first clock that the D end ground connection of said first d type flip flop, input end of clock are connected to phase-locked loop output, Q end link to each other with the D end of second d type flip flop and the grid of NMOS pipe respectively; The clock input of said second d type flip flop is connected to first clock of phase-locked loop output.
Said impulsive synchronization module also comprises 3d flip-flop and NAND gate; Two inputs of said NAND gate link to each other with the Q end of said second d type flip flop, the Q end of 3d flip-flop respectively; The output of said NAND gate links to each other with the D of 3d flip-flop end, and the input end of clock of said 3d flip-flop is connected to first clock of said phase-locked loop output.
Said phase deflection correction module is according to the first clock generating framing signal, and said synchronizing signal is carried out bit comparison mutually with framing signal, and when there is phase deviation in both, and synchronizing signal is carried out phase correction and exported with the base band clock.
Said data statistics module comprises counter, comparator and reference circuit; Said counter input is connected to the output and first clock of phase deflection correction module respectively, and said comparator input is connected to counter output respectively, reference circuit output links to each other with controllable gain amplifier with first clock, output.
Said first clock is 3 times a base band clock.
Said pulse ultra wideband receiver adopts cmos device to realize.
The beneficial effect of the present invention and prior art contrast is: the present invention adopts the pulse ultra wideband receiver of asynchronous triggering; Utilize the simple numerical logical circuit to realize the reception of ultra-wideband pulse; The power consumption of having avoided traditional synchronized sampling method of reseptance in ultra-broadband signal receives, to bring is big, complicated circuit, limitation such as not easy of integration; Have circuit and simply be easy to advantage integrated, low in energy consumption, particularly suitable in ultra-wideband pulse communication.The present invention can significantly reduce the power consumption and the complexity of receiving circuit in correct reception signal, help chip and realize.This receiver can exchange the reduction of pulse UWB communication system energy consumption with less transmit signal energy cost for, and reduces the realization difficulty of circuit.
Description of drawings
Fig. 1 is the theory diagram of the pulse ultra wideband receiver of the specific embodiment of the invention;
Fig. 2 is the structural representation of the pulse ultra wideband receiver of the specific embodiment of the invention;
Fig. 3 is the structural representation of the impulsive synchronization module of the specific embodiment of the invention;
Fig. 4 is the signal sequence sketch map of the impulsive synchronization module of the specific embodiment of the invention;
Fig. 5 is the physical circuit sketch map of the pulse ultra wideband receiver of the specific embodiment of the invention;
Fig. 6 is the structural representation of the phase-locked loop of the specific embodiment of the invention.
Embodiment
Below through concrete execution mode and combine accompanying drawing that the present invention is explained further details.
The present invention takes all factors into consideration communication theory and Circuit theory, and combines the characteristics of UWB technology, proposes a kind of new signal receiver structure---and asynchronous triggering receives (asynchronous triggerreceiving).
As shown in Figure 1, a kind of pulse ultra wideband receiver comprises interconnective controllable gain amplifier 1 and triggers receiver 2.1 pair of radiofrequency signal that receives of said controllable gain amplifier is amplified and is exported to and trigger receiver 2; Said triggering receiver 2 judges whether the energy of the radiofrequency signal after amplifying surpasses preset value; If just carry out asynchronous triggering, obtain high level (being data 1), otherwise obtain low level (data 0).
As shown in Figure 2, said triggering receiver comprises impulsive synchronization module, phase deflection correction module and phase-locked loop (PLL).Said impulsive synchronization module is coupling between controllable gain amplifier and the phase deflection correction module, and said phase-locked loop is exported the first clock clk3 to impulsive synchronization module, phase deflection correction module.Said impulsive synchronization device obtains synchronizing signal and exports to the phase deflection correction module under the first clock clk3 radiofrequency signal after amplifying being carried out impulsive synchronization; Said phase deflection correction module is carried out the correction of phase deviation to synchronizing signal under the first clock clk3, obtained the base band data RXD that demodulates.Among Fig. 2, RFI is the radiofrequency signal that receiver receives.
As shown in Figure 3, said impulsive synchronization module comprises PMOS pipe M1, NMOS pipe M2, the first capacitor C d, delayer, first d type flip flop, second d type flip flop.The source electrode of said PMOS pipe M1 connects power supply, and the grid of PMOS pipe M1 links to each other with the output of said controllable gain amplifier.The drain electrode of said PMOS pipe M1 links to each other after the first capacitor C d ground connection with the drain electrode of NMOS pipe M2.The source ground of said NMOS pipe M2.The serial connection point of said PMOS pipe M1 of the input termination of said delayer and NMOS pipe M2, the set S end of said first d type flip flop of output termination.The D end ground connection of said first d type flip flop, clock input R termination have the first clock clk3 of phase-locked loop output, Q end to link to each other with the D end of second d type flip flop and the grid of NMOS pipe M2 respectively.The clock input R of said second d type flip flop is connected to the first clock clk3 of phase-locked loop output.The Q end of said second d type flip flop can be as the output of impulsive synchronization module.
Delayer can be when pulse arrives; Make first d type flip flop Q end time-delay set; So that when said pulse arrives, can charge to the said first capacitor C d, and after this first d type flip flop set is accomplished, manage M2 to capacitor discharge through said NMOS through said PMOS pipe M1.Delayer can make the d type flip flop can be by burst pulse set reliably.When burst pulse arrives, the first capacitor C d is charged, just can manage M2 after the process certain time-delay is accomplished Q1 set and make first capacitor C d discharge through NMOS through PMOS pipe M1.
Said first clock is 3 times a base band clock.The impulsive synchronization module is operated under the base band clock of 3 frequencys multiplication, and the use frequency is that the first clock clk3 of three times of base band clock clk carries out synchronously.Promptly handle the 1bit data, be convenient to phase deviation and correct, make the phase deflection correction module of the back level three kinds of states of can distinguishing in advance, aim at, lag behind with 3 clock cycle.
As shown in Figure 4.When the grid in of PMOS pipe M1 had the pulse input, PMOS pipe M1 and NMOS pipe M2 carried out hard decision to input, when the grid in of PMOS pipe M1 is low level pulse, and PMOS pipe M1 conducting, the drain electrode in ' of PMOS pipe M1 is output as high level.Carry out after shaping and the certain delay first d type flip flop that contains asynchronous reset functionality being carried out set through delayer, make Q1 be output as " 1 ", feed back to the grid of NMOS pipe M2 simultaneously, the first capacitor C d is discharged.When the rising edge of the first clock clk3 arrives, Q1 is carried out " cleaning ", make it to become " 0 ".Second trigger is caught the output of Q1, reaches Q2.
Under the ideal situation, the high level of a Q2 just possibly appear in per 3 clock cycle (1bit data).Consider special circumstances, when pulse arrives near the clk3 rising edge, might cause Q2 in adjacent 2 clock cycle, to be high level.Therefore, as shown in Figure 3, said impulsive synchronization module also can be set up 3d flip-flop and NAND gate.Cancellation the 2nd high level wherein only keeps 1 high level when above-mentioned situation appears in Q2.Two inputs of said NAND gate link to each other with the Q end of said second d type flip flop, the Q end of 3d flip-flop respectively; The output of said NAND gate links to each other with the D of 3d flip-flop end, and the clock input R termination of said 3d flip-flop has the first clock clk3 of said phase-locked loop pll output.At this moment, the Q of said 3d flip-flop end can be as the output of impulsive synchronization module
Said triggering receiver operation is handled the one digit number certificates with three clock cycle under frequency tripling clock signal (clk3), correct the module three kinds of states of can distinguishing in advance, aim at, lag behind with the phase deviation of level after an action of the bowels.
Said phase deflection correction module produces framing signal according to the first clock clk3, and said synchronizing signal is carried out bit comparison mutually with framing signal, and when there is phase deviation in both, and synchronizing signal is carried out phase correction and exported with the base band clock.The phase deflection correction module can be corrected the clock phase deviation between the transceiver, with the reception mistake of avoiding the clock phase deviation to cause.
The phase deflection correction module is a totally digital circuit.The phase deflection correction module can produce the framing signal (its pulsewidth equals the clk3 clock cycle) that cycle T b, duty ratio that one-period equals synchronizing signal equal 1/2 according to the first clock clk3.The phase deflection correction module is carried out bit comparison mutually with synchronizing signal with framing signal, distinguishes leading, the three kinds of states of aiming at, lag behind, the phase place of adjustment synchronizing signal, and (clk) latchs output with the base band clock.When the then adjustment forward during 1 clock cycle of the leading framing signal of synchronizing signal, on the contrary then adjustment backward.Only go to judge 3 data of current and front and back in the adjacent clock cycle of synchronizing signal during for high level when framing signal, and their fetch logics or, latch output with base band clock clk at last.Like this, can be corrected by this circuit less than the skew of 1/3 Tb.The UWB system generally is applied to non-high-speed mobile equipment, so skew is generally less, and most phase assistant generals are repaired.
As shown in Figure 2; Said triggering receiver also comprises data statistics module; Said data statistics module is coupling between phase deflection correction module and the controllable gain amplifier; Said data statistics module also receives the first clock clk3 of phase-locked loop output; Said data statistics module is added up the number of the high level of phase deflection correction module output in the certain hour cycle (for example continuous 32 clk3 are in the clock cycle) and is compared the back with fiducial value and produces corresponding gain control signal, exports the gain control input of controllable gain amplifier to.If the very few gain that just increases VGA of the number of the high level of being remembered, on the contrary then reduce,, the number of high level gets into locking when falling into fiducial value (promptly respectively accounting for 50% corresponding to high level and low level number).This moment system transmissions average information H (X) maximum.
As shown in Figure 5; Said data statistics module comprises counter, comparator and reference circuit; Said counter input is connected to the output and the first clock clk3 of phase deflection correction module respectively, and said comparator input is connected to counter output respectively, reference circuit output links to each other with controllable gain amplifier with the first clock clk3, output.
Said counter is counted the number of the high level of interior phase deflection correction module output of certain hour cycle (in for example continuous 32 clk3 clock cycle), and count results is delivered to said comparator.Comparator compares count results and the reference signal of exporting from reference circuit under the control of the first clock clk3, produces corresponding gain control signal according to comparative result and is sent to said controllable gain amplifier (VGA).
As shown in Figure 6, said phase-locked loop pll comprises tri-frequency divider, and the hungry type chain of inverters voltage controlled oscillator (VCO) of the phase frequency detector (PFD) that is connected in series successively, charge pump (CP) and electric current.
The first clock signal clk3 output of the hungry type chain of inverters voltage controlled oscillator of said electric current (VCO) links to each other with the feedback signal input of said phase frequency detector (PFD); This phase frequency detector (PFD) also has the input of a base band clock signal (clk), and this clock multiplier phase-locked loop (PLL) produces the first clock signal clk3 (frequency tripling clock) with said base band clock (clk).Simultaneously; Said charge pump (CP) input links to each other with the output of said phase frequency detector (PFD); And charge pump (CP) output links to each other with the input control end of the hungry type chain of inverters voltage controlled oscillator of said electric current (VCO); Simultaneously through a capacitance-resistance (RC network) sequential circuit ground connection, to realize the loop LPF.
Above-mentioned triggering receiver adopts cmos device to realize.Particularly, by dynamically and the static cmos logic circuit form, also be no steady state short circuit current, so its power consumption is less.
Above-mentioned pulse ultra wideband receiver can be integrated in the chip, also can integrated transmitter in the chip, realize that baseband digital signal is to the mapping between the UWB pulse signal.The RC network of phase-locked loop is also outside chip.
Pulse ultra wideband receiver implementation complexity of the present invention is lower, does not exist to be difficult to realize or integrated particular device (like the high-precision analog delay line of using in the simulation correlation reception); On the other hand; The present invention can drop to the operating frequency of circuit that minimum (the every reception of receiver 1bit data only need trigger upset 1 time; Receive than digital correlation and to have reduced Nb doubly), thereby reduced energy consumption (dissipation energy) Ed that receiver is handled the unit bit signal.Consider Electro Magnetic Compatibility, the spectrum width W of regulation UWB signal is at least 500MHz, and power spectral density must be enough low so that do not disturb other narrowband systems, and therefore, the energy consumption Ed of pulse ultra wideband receiver of the present invention will be starkly lower than the digital correlation receiver.With relevant the comparing of simulation, but pulse ultra wideband receiver of the present invention has good realizability and integration; Receive with digital correlation and to compare, pulse ultra wideband receiver of the present invention can exchange that the remarkable reduction of circuit energy consumption Ed---10 times of the every reductions of receiver sample rate, the Eb expense only increases about 1dB with less signal energy Eb cost for.
Be that 3 times base band clock is that example describes with first clock above.Certain first clock also can be 4,5 times base band clock.But 3 times base band clock is a kind of minimalist program, can correct phase place comparatively completely, so generally adopt 3 times base band clock.
Be that example describes with counter to the high level of continuous 32 clk3 in the clock cycle above, count cycle that certainly also can corresponding as required adjustment counter.
Above content is to combine concrete preferred implementation to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (8)
1. pulse ultra wideband receiver; It is characterized in that: comprise interconnective controllable gain amplifier and trigger receiver; Said controllable gain amplifier amplifies the radiofrequency signal that receives and exports to the triggering receiver; Said triggering receiver judges whether the energy of the radiofrequency signal after amplifying surpasses preset value; If just carry out asynchronous triggering, obtain high level, otherwise obtain low level, said triggering receiver comprises impulsive synchronization module, phase deflection correction module and phase-locked loop; Said impulsive synchronization module is coupling between controllable gain amplifier and the phase deflection correction module; Said phase-locked loop is exported first clock to impulsive synchronization module, phase deflection correction module, and said impulsive synchronization device obtains synchronizing signal and exports to the phase deflection correction module under first clock radiofrequency signal after amplifying being carried out impulsive synchronization, and said phase deflection correction module is carried out the correction of phase deviation to synchronizing signal under first clock.
2. pulse ultra wideband receiver according to claim 1; It is characterized in that: also comprise data statistics module; Said data statistics module is coupling between phase deflection correction module and the controllable gain amplifier; Said data statistics module also receives first clock of phase-locked loop output; Said data statistics module statistics compares the corresponding gain control signal of back generation at the number of certain hour high level of phase deflection correction module output in the cycle and with fiducial value, exports the gain control input of controllable gain amplifier to.
3. pulse ultra wideband receiver according to claim 2; It is characterized in that: said impulsive synchronization module comprises PMOS pipe (M1), NMOS pipe (M2), first electric capacity (Cd), delayer, first d type flip flop, second d type flip flop; The source electrode of said PMOS pipe (M1) connects power supply; Grid links to each other with the output of said controllable gain amplifier, and the drain electrode of the drain electrode of said PMOS pipe (M1) and NMOS pipe (M2) links to each other after first electric capacity (Cd) ground connection, and said NMOS manages the source ground of (M2); Set (S) end of the serial connection point of said PMOS pipe of the input termination of said delayer (M1) and NMOS pipe (M2), said first d type flip flop of output termination, first clock that the D end ground connection of said first d type flip flop, clock input (R) termination have phase-locked loop output, Q end link to each other with the D end of second d type flip flop and the grid of NMOS pipe (M2) respectively; The clock input (R) of said second d type flip flop is connected to first clock of phase-locked loop output.
4. pulse ultra wideband receiver according to claim 3; It is characterized in that: said impulsive synchronization module also comprises 3d flip-flop and NAND gate; Two inputs of said NAND gate link to each other with the Q end of said second d type flip flop, the Q end of 3d flip-flop respectively; The output of said NAND gate links to each other with the D of 3d flip-flop end, and clock input (R) termination of said 3d flip-flop has first clock of said phase-locked loop (PLL) output.
5. pulse ultra wideband receiver according to claim 4; It is characterized in that: said phase deflection correction module is according to the first clock generating framing signal; And said synchronizing signal carried out bit comparison mutually with framing signal; And when there is phase deviation in both, synchronizing signal is carried out phase correction and exported with the base band clock.
6. pulse ultra wideband receiver according to claim 5; It is characterized in that: said data statistics module comprises counter, comparator and reference circuit; The output of phase deflection correction module and first clock input to said counter, and counter is exported, reference circuit exports and first clock inputs to said comparator, said comparator exports controllable gain amplifier to.
7. according to the arbitrary described pulse ultra wideband receiver of claim 1-6, it is characterized in that: said first clock is 3 times a base band clock.
8. according to the arbitrary described pulse ultra wideband receiver of claim 1-6, it is characterized in that: said triggering receiver adopts cmos device to realize.
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| WO2011035493A1 (en) * | 2009-09-28 | 2011-03-31 | 东南大学 | High-speed sampling and low-precision quantification pulse ultra-wideband wireless communication method |
| CN102360070B (en) * | 2011-06-10 | 2013-04-03 | 中国科学技术大学 | Receiving apparatus for ultra wideband impulse signal and ultra wideband impulse radar system |
| IL246991B (en) | 2016-07-27 | 2018-02-28 | Elbit Systems Land & C4I Ltd | Reduction of power consumption in integral ultra-wideband power amplifiers |
| CN109271812B (en) * | 2018-10-25 | 2022-04-05 | 河海大学常州校区 | Arbiter PUF circuit based on current starvation |
| CN109831401B (en) * | 2019-03-19 | 2021-04-13 | 西安电子科技大学 | Modulator and method based on common reference in MIMO system |
| CN113015087B (en) * | 2021-02-23 | 2022-08-23 | 四川中电昆辰科技有限公司 | Ultra-wideband positioning tag and positioning signal transmitting method |
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| US5345471A (en) * | 1993-04-12 | 1994-09-06 | The Regents Of The University Of California | Ultra-wideband receiver |
| JP3785487B2 (en) * | 2004-10-28 | 2006-06-14 | 学校法人東京電機大学 | Ultra-wideband pulse receiver |
| JP2007116621A (en) * | 2005-10-24 | 2007-05-10 | Samsung Electronics Co Ltd | Wireless communication apparatus |
| CN101252564A (en) * | 2008-03-31 | 2008-08-27 | 张剑 | Code quadrature transmitting reference modem system in ultra-wideband communication and using method thereof |
| CN101262286A (en) * | 2008-04-19 | 2008-09-10 | 桂林电子科技大学 | A novel ultra-broadband (UWB) energy detection circuit |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5345471A (en) * | 1993-04-12 | 1994-09-06 | The Regents Of The University Of California | Ultra-wideband receiver |
| JP3785487B2 (en) * | 2004-10-28 | 2006-06-14 | 学校法人東京電機大学 | Ultra-wideband pulse receiver |
| JP2007116621A (en) * | 2005-10-24 | 2007-05-10 | Samsung Electronics Co Ltd | Wireless communication apparatus |
| CN101252564A (en) * | 2008-03-31 | 2008-08-27 | 张剑 | Code quadrature transmitting reference modem system in ultra-wideband communication and using method thereof |
| CN101262286A (en) * | 2008-04-19 | 2008-09-10 | 桂林电子科技大学 | A novel ultra-broadband (UWB) energy detection circuit |
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