CN101502000B - 低输出偏斜双倍数据速率串行编码器 - Google Patents

低输出偏斜双倍数据速率串行编码器 Download PDF

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CN101502000B
CN101502000B CN2007800293195A CN200780029319A CN101502000B CN 101502000 B CN101502000 B CN 101502000B CN 2007800293195 A CN2007800293195 A CN 2007800293195A CN 200780029319 A CN200780029319 A CN 200780029319A CN 101502000 B CN101502000 B CN 101502000B
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mddi
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柯蒂斯·D·马斯菲尔德特
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Qualcomm Inc
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Abstract

本发明提供一种双倍数据速率(DDR)串行编码器。在一个方面中，所述DDR串行编码器包含用于确保无假信号编码器输出的非无假信号多路复用器及数字逻辑。通过使用非无假信号多路复用器，所述编码器的大小及复杂性显著减小。在另一方面中，所述DDR串行编码器在最终寄存器级与编码器输出之间具有单个逻辑层，由此导致输出偏斜减少且链路速率增加。

Description

低输出偏斜双倍数据速率串行编码器
相关申请交叉参考案
本申请案主张优先于2005年11月23日提出申请的名称为“双倍数据速率串行编码器(Double Data Rate Serial Encoder)”的第11/285,397号申请案，所述申请案又主张优先于以下临时申请案：2004年11月24日提出申请的名称为“MDDI主机核心设计(MDDI Host Core Design)”的第60/630,853号、2004年11月30日提出申请的名称为“移动显示数字接口主机相机接口装置(Mobile Display Digital InterfaceHost Camera Interface Device)”的第60/631,549号、2004年12月2日提出申请的名称为“相机MDDI主机装置(Camera MDDI Host Device)”的第60/632,825号、2004年12月2日提出申请的名称为“MDDI概述(MDDI Overview)”的第60/633,071号、2004年12月1日提出申请的名称为“MDDI主机核心垫设计(MDDI Host Core PadDesign)”的第60/633,084号及2004年12月2日提出申请的名称为“MDDI主机控制器的实施方案(Implementation of the MDDI Host Controller)”的第60/632,852号，所述这些申请案被让与给本发明的受让人且其全文以引用的方式明确地并入本文中。
本申请案还与2004年7月6日颁布的名称为“产生及实施用于高速度数据传送的通信协议及接口(Generating and Implementing a Communication Protocol andInterface for High Speed Data Transfer)”的第6,760,772 B2号共同受让美国专利有关，所述专利的揭示内容以引用方式并入本文中。
技术领域
本发明通常涉及用于高数据速率串行通信链路的串行编码器。更特定来说，本发明涉及用于移动显示数字接口(MDDI)链路的双倍数据速率串行编码器。
背景技术
在互连技术领域中，对不断增加的数据速率(尤其是与视频呈现相关的数据速率)的要求继续增长。
移动显示数字接口(MDDI)是能够在主机与客户端之间的短程通信链路上实现极高速度的数据传送的成本有效、低电力消耗传送机制。MDDI需要最少仅四根导线加上电力用于递送高达每秒3.2十亿位的最大带宽的双向数据传送。
在一个应用中，MDDI通过显著减少跨越手机铰链延伸以互连数字基带控制器与LCD显示器及/或相机的导线的数目来增加翻盖手机的可靠性并降低其电力消耗。此导线减少还允许手机制造者通过简化翻盖手机或滑盖手机设计而降低开发成本。
MDDI是串行传送协议，且因此需要串行化并行接收的用于在MDDI链路上传输的数据。2005年12月23日提出申请的名称为“双倍数据速率串行编码器(DoubleData Rate Serial Encoder)”的第11/285,397号美国专利申请案描述了具有无假信号输出的MDDI双倍数据速率(DDR)串行编码器。所述无假信号输出串行编码器得益于用格雷(Gray)码输入选择序列的先验知识设计的无假信号多路复用器。此输入选择序列的先验知识实现多路复用器大小的减小及因此DDR串行编码器大小的减小。
然而，可在数个方面对美国申请案第11/285,397号中描述的DDR串行编码器设计作出改善。在一个方面中，应注意在美国申请案第11/285,397号中描述的DDR串行编码器中所用的无假信号多路复用器在大小上仍大于非无假信号多路复用器。在另一方面中，最终寄存器级与编码器输出之间的多个逻辑层(其是贡献较大输出偏斜及较低链路速率的因子)可显著减少。
因此，所需要的是具有减小的大小、复杂性及输出偏斜的MDDI DDR串行编码器。还需要具有无假信号输出的MDDI DDR串行编码器。
发明内容
本文中提供一种双倍数据速率(DDR)串行编码器。
在一个方面中，所述DDR串行编码器包含用于确保无假信号编码器输出的非无假信号多路复用器及数字逻辑。通过使用非无假信号多路复用器，编码器的大小及复杂性显著减少。
在另一方面中，所述DDR串行编码器在最终寄存器级与编码器输出之间具有单个逻辑层及减少的从所述最终寄存器级到所述编码器输出路径的数目，由此导致输出偏斜减少且链路速率增加。从所述最终寄存器级到编码器输出的路径数目的减少还简化输出偏斜分析。
下文将参照附图来详细描述本发明的其它实施例、特征及优点、以及本发明各种实施例的结构及操作。
附图说明
并入本文中并形成本说明书一部分的附图图解说明本发明并与本说明一起进一步用于解释本发明的原理及使所属技术领域的技术人员能够制作并利用本发明。
图1是图解说明使用移动显示数字接口(MDDI)接口的实例环境的方框图。
图2是图解说明根据图1实例的实施例的MDDI链路互连的方框图。
图3是图解说明MDDI串行编码器的电路图。
图4A-B图解说明信号偏斜的实例。
图5是图解说明根据本发明实施例的MDDI串行编码器的方框图。
图6是图解说明根据本发明另一实施例的MDDI串行编码器的电路图。
图7是与图6的MDDI串行编码器的信号相关的实例定时图。
图8是图解说明根据本发明的其它实施例的MDDI串行编码器的电路图。
图9是与图8的MDDI串行编码器的信号相关的实例定时图。
将参照附图来描述本发明。元件首先出现的图示通常由对应参考编号中的最左一个或多个数位指示。
具体实施方式
本说明书揭示一个或一个以上并有本发明特征的实施例。所揭示的一个或多个实施例仅例示本发明。本发明的范围并不限于所述所揭示的一个或多个实施例。本发明由本发明所附的权利要求书来界定。
所描述的一个或多个实施例及说明书中提及的“一个实施例”、“实施例”、“实例实施例”等指示所述的一个或多个实施例可包含特定特征、结构或特性，但每一实施例可能不必包括所述特定特征、结构或特性。而且，所述词语未必是指同一实施例。此外，在结合实施例描述特定特征、结构或特性时，应理解，无论是否明确描述，结合其它实施例实施所述特征、结构或特性均在所属技术领域的技术人员的知识范围内。
本发明实施例可实施于硬件、固件、软件或其任何组合中。本发明实施例还可实施为存储在机器可读媒体上的指令，所述指令可由一个或一个以上处理器读取并执行。机器可读媒体可包含用于存储或传输呈可由机器(例如，计算装置)读取形式的信息的任何机制。例如，机器可读媒体可包含只读存储器(ROM)；随机存取存储器(RAM)；磁盘存储媒体；光学存储媒体；快闪存储器装置；电、光、声或其它形式的传播信号(例如，载波、红外信号、数字信号等)及其它。此外，在本文中可将固件、软件、例程、指令描述为执行某些动作。然而，应了解，此类说明仅是出于方便且事实上此类动作由计算装置、处理器、控制器或执行固件、软件、例程、指令等的其它装置产生。
移动显示数字接口(MDDI)
移动显示数字接口(MDDI)是能够在主机与客户端之间的短程通信链路上实现极高速度串行数据传送的成本有效、低电力消耗的传送机制。
在下文中，将相关于移动电话的上翻盖中所包含的相机模块呈现MDDI的实例。然而，所属一个或多个相关技术领域的技术人员将明了任何具有功能等效于相机模块的特征的模块可易于被替代及用于本发明的各种实施例中。
此外，根据本发明实施例，MDDI主机可包括可得益于使用本发明的数个类型装置中的一者。例如，主机可以是呈手持式、膝上型、或类似移动计算装置形式的便携式计算机。其还可以是个人数据助理(PDA)、寻呼装置、或众多无线电话或调制解调器中的一者。另一选择为，主机可以是便携式娱乐装置或呈现装置，例如便携式DVD或CD播放机、或玩游戏装置。此外，所述主机可作为主机装置或控制元件驻留在各种其它广泛使用或已规划的并期望与客户端具有一高速度通信链路的商业产品中。例如，主机可用来以高速率将数据从视频记录装置传送到基于存储装置的客户端以改善其响应，或者传送到高分辨率的更大屏幕以供呈现。例如电冰箱等电器并入有单板库存或计算系统及/或与其它家用装置的蓝牙连接，其在以网络或蓝牙连接模式操作时可具有改善的显示能力，或者当电子计算机或控制系统(主机)驻留在机柜中的其它位置时可降低对室内显示器(为客户端)及小键盘或扫描器(客户端)的布线需要。一般来说，所属技术领域的技术人员应了解，有很多种现代电子装置及电器可得益于使用此接口，且能够利用新增的或现有的连接器或电缆中所具有的有限数目导体以更高数据速率的信息传输来翻新过时的装置。同时，MDDI客户端可包括各种适用于向终端用户呈现信息或从用户向主机呈现信息的装置。例如，并入护目镜或眼镜中的微显示器、内建于帽子或护盔中的投影装置、内建于车辆中(例如车窗或挡风玻璃中)的小屏幕或甚至全息元件，或各种扬声器、头戴式耳机、或用于呈现高质量声音或音乐的音响系统。其它呈现装置包含用于呈现会议信息或呈现电影及电视图像的投影机或投影装置。其它实例包含使用触摸垫或敏感装置、语音识别输入装置、安全扫描器等等，所述装置可用来利用除用户的触摸或声音外几乎没有其它实际“输入”来传送来自装置或系统用户的大量信息。此外，计算机的坞站及无线电话的车用免持套件或桌面免持套件及支座可用作与终端用户或与其它装置及设备的接口装置，并采用客户端(例如鼠标等输出或输入装置)或主机来帮助进行数据传输，尤其当涉及高速度网络时。然而，所属技术领域的技术人员将易于认识到，本发明并非限于这些装置，还存在许多其它市售的及人们提议使用的装置，所述装置旨在在存储及传输方面或在回放时的呈现方面为终端用户提供高质量图像及声音。本发明适用于提高各种元件或装置之间的数据通量，以容纳为实现所需用户感受所需的高数据速率。
图1是图解说明使用MDDI接口的实例环境的方框图。在图1的实例中，MDDI用于互连横跨翻盖手机100的铰链的模块。此处，必须注意，尽管将在具体实例(例如，翻盖手机中的MDDI互连)的背景中描述本发明的某些实施例，但这样做仅是用于图解说明的目的且不应用来限制本发明于此类实施例。如所属一个或多个相关技术领域的技术人员基于本文中的教示内容所理解，本发明实施例可用于包含可得益于具有MDDI互连的任何装置的其它装置中。
参照图1，翻盖手机100的下翻盖部分102包含移动台调制解调器(MSM)基带芯片104。MSM 104是数字基带控制器。翻盖手机100的上翻盖部分114包含液晶显示器(LCD)模块116及相机模块118。
还是参照图1，MDDI链路110将相机模块118连接到MSM 104。通常，将MDDI链路控制器集成在相机模块118及MSM 104中的每一者中。在图1的实例中，MDDI主机122被集成在相机模块112中，同时MDDI客户端106驻留在MDDI链路110的MSM侧上。通常，MDDI主机是MDDI链路的主控制器。在图1的实例中，来自相机模块118的像素数据在被传输到MDDI链路110上之前由MDDI主机122接收并将其格式化为MDDI包。MDDI客户端106接收所述MDDI包并将其重转换为与相机模块118产生的格式相同的像素数据。然后，将像素数据发送到MSM 104中的适当块以进行处理。
还是参照图1，MDDI链路112将LCD模块116连接到MSM 104。在图1的实例中，MDDI链路112使集成在MSM 104中的MDDI主机108与集成在LCD模块116中的MDDI客户端120互连。在图1的实例中，MSM 104的图形控制器所产生的显示数据在被传输到MDDI链路112上之前由MDDI主机108接收并将其格式化为MDDI包。MDDI客户端120接收MDDI包并将其重转换为显示数据以供LCD模块116使用。
图2是图解说明根据图1的实例的MDDI链路互连110的方框图。如上文所述，MDDI链路110功能中的一者是将像素数据从相机模块118传送到MSM 104。因此，在图2的实施例中，帧接口206将相机模块118连接到MDDI主机122。帧接口206用于将像素数据从相机模块118传送到MDDI主机122。
通常，相机模块118通过并行接口接收来自相机的像素数据、存储所述像素数据且然后当主机准备好时将其传送到MDDI主机122。MDDI主机122将所接收的像素数据封装为MDDI包。然而，为使MDDI主机122能够将像素数据传输到MDDI链路110上，必须对MDDI包进行串行化。
在图2的实施例中，集成在MDDI主机122内的串行化器模块202用来将MDDI包串行地移出到MDDI链路110上。在MDDI链路110的MSM端处，集成在MDDI客户端106内的并行化器模块204从经由MDDI链路110接收的串行数据重构MDDI包。然后，MDDI客户端106去除MDDI封装且经由帧接口208将并行像素数据传送到MSM 104的适当块。
MDDI串行编码器
图3是图解说明MDDI串行编码器300的电路图。在2005年11月23日提出申请的名称为“双倍数据速率串行编码器(Double Data Rate Serial Encoder)”的第11/285,397号美国申请案中更详细地描述了MDDI串行编码器300。串行编码器300包含使用触发器320及322图解说明的最终数据寄存器级、使用触发器314、316及318图解说明的选择输入寄存器级及无假信号多路复用器电路324。
最终数据寄存器级触发器320及322分别接收数据输入信号308及310。在一个实施例中，数据输入信号308及310各自为4位。因此，触发器320及322各自为4位触发器。在其它实施例中，触发器320及322可用四个2位触发器或八个1位触发器来代替。如图3中所图解说明，触发器320及322为D触发器，但如所属技术领域的技术人员基于本文中的教示内容所理解，还可使用其它类型的触发器或寄存器。触发器320及322受时钟信号312控制且在时钟信号312的每一上升边缘处更新其输出。
选择输入寄存器级触发器314、316及318分别接收选择输入信号sel(2)302、sel(1)304及sel(0)306。选择输入信号302、304及306通常由计数器提供且用来选择多路复用器电路324的输入。在一个实施例中，选择信号302、304及306是根据格雷码序列产生的，所述格雷码序列为多路复用器电路324先验已知的，由此允许无假信号多路复用器输出。触发器314、316及318为D触发器，但如所属技术领域的技术人员基于本文中的教示内容所理解，还可使用其它类型的触发器。触发器314、316及318也受时钟信号312控制，其中触发器318在时钟信号312的上升边缘处更新其输出，且触发器314及316在时钟信号312的下降边缘处更新其输出。
多路复用器电路324接收来自最终数据寄存器级的数据输入信号及来自选择输入寄存器级的输入选择信号并产生串行编码器300的输出334。多路复用器电路324使用格雷码输入选择序列的先验知识产生无假信号编码器输出。多路复用器电路324包含四个逻辑层326、328、330及332，其使最终数据寄存器级(触发器320及322)及选择输入寄存器级(触发器318、320及322)与编码器输出334分离。逻辑层326在从选择输入寄存器级到编码器输出的某些路径上包含反相器电路。逻辑层326经由互连耦合到逻辑层328，所述逻辑层328包含多个“与”门。而逻辑层328又经由互连耦合到逻辑层330。逻辑层330包含多个提供逻辑层332的输入的“或”门。逻辑层332包含提供串行编码器的输出334的“或”门。
应注意，多路复用器电路324的四个逻辑层326、328、330及332是基于组合逻辑且不被时钟信号驱动。因此，在从最终数据寄存器级及/或选择输入寄存器级到编码器输出的不同路径上的信号传播延迟可不同。此外，信号传播延迟可根据编码器电路中的温度及/或过程变化而不同，从而使其难于监视及/或对其进行补偿。
通常，在到编码器输出的路径上具有不同信号传播延迟导致被称作“输出偏斜”的结果，其中实际编码器输出相对于所需标称输出偏斜或失真。输出偏斜还可由贡献编码器输出的单个信号的偏斜而产生。
图4A-B图解说明信号偏斜的实例。图4A图解说明实例信号400的偏斜，由此，下降及/或上升边缘可早于或晚于其应该理想发生的时间发生。图4B图解说明两个信号输出1与输出2之间的偏斜。输出1及输出2由经同步化输入信号402及402分别通过实例性电路414的路径406及408进行传播而产生，其中路径406及408具有不同的信号传播延迟。图4B中图解说明为“tsk”的信号输出1与输出2之间的偏斜表示理想地将同时发生的信号输出1与输出2之间的时间差量值。应注意，信号输出1与输出2之间的偏斜可导致实例性电路414的输出412处的输出偏斜。
在某些情况中，输出偏斜可致使最大MDDI链路速率降低。因此，显而易见地，应最小化输出偏斜。
低输出偏斜MDDI串行编码器
根据本发明，通过最小化贡献输出偏斜的因子的效应来减少输出偏斜。在一个方面中，输出偏斜受贡献编码器输出的每一信号(来自最终数据寄存器级及/或选择输入寄存器级)的个别偏斜的影响。在另一方面中，输出偏斜与这些个别信号偏斜的量值成比例，所述个别信号偏斜量值又与其相应信号路径的长度(其为到达编码器输出的连续逻辑层数目的函数)成比例。
因此，可通过最小化以下来减少输出偏斜：(1)贡献编码器输出的信号的数目(来自最终数据寄存器级及/或选择输入寄存器级)，及(2)从最终数据寄存器级及/或选择输入寄存器级到编码器输出的逻辑层数目。
图5是图解说明根据本发明实施例的MDDI串行编码器500的方框图。串行编码器500包含非无假信号多路复用器506及同步化电路510。
非无假信号多路复用器506接收数据输入信号504及输入选择信号502并产生输出信号508。在一实施例中，数据输入信号504包含8位信号。在其它实施例中，数据输入信号504包含两个4位信号、四个2位信号或8个1位信号。输入选择信号502控制多路复用器506将所接收的数据输入信号中的一者耦合到多路复用器的输出。通常，输入选择信号502的数目N是如此以使得2N等于信号504中数据位的数目。在图5中，输入选择信号502的数目为3，从而使多路复用器506为一8:1多路复用器。
由于多路复用器506的输出508可以为非无假信号，因此串行编码器500可被显著简化。在一个方面中，可允许在任何时候且不仅在其不被选择用于输出时切换输入信号504中的数据位，如在无假信号多路复用器中。在另一方面中，由输入选择信号502携载的输入选择序列不再需要依附于格雷码序列。
因此，为产生无假信号编码器输出，使用同步化电路510来确保输出508中的任何假信号均在编码器输出512处被去除。在一个实施例中，同步化电路510包含能够使贡献编码器输出的信号相对于彼此具有最小偏斜的时钟驱动最终数据寄存器级。另外，最终数据寄存器级是远离编码器输出的极少数目的逻辑层，此进一步减少输出偏斜。
图6是图解说明根据本发明另一实施例的MDDI串行编码器600的电路图。
串行编码器600包含使用触发器620图解说明的数据寄存器级、使用触发器612、614及616图解说明的选择输入寄存器级、多路复用器622及同步化电路626。
数据寄存器级触发器620接收数据输入信号610。在一个实施例中，数据输入信号610包含8位信号。因此，触发器620是8位触发器。在其它实施例中，触发器620可用两个4位触发器、四个2位触发器或八个1位触发器来代替。如在图6中所图解说明，触发器620是D触发器，但如所属技术领域的技术人员基于本文中的教示内容所理解，还可使用其它类型的触发器或寄存器。
选择输入寄存器级触发器612、614及616分别接收选择输入信号sel(2)602、sel(1)604及sel(0)606。选择输入信号602、604及606通常由计数器来提供且用来选择多路复用器622的输入。选择信号602、604及606不需要依附于任何类型的输入选择序列，举例来说例如格雷码序列。触发器612、614及616为D触发器，但如所属技术领域的技术人员基于本文中的教示内容所理解，还可使用其它类型的触发器。
多路复用器622接收来自数据寄存器级的数据输入信号及来自选择输入寄存器级的输入选择信号并产生输出信号624。在一个实施例中，多路复用器622为8:1多路复用器。
多路复用器622是非无假信号多路复用器。换句话说，假信号可发生在多路复用器622的输出624处。因此，将多路复用器622的输出624提供到同步化电路626以确保在编码器输出642处去除输出624中的任何假信号。
同步化电路626包含使用“异或”门628及630图解说明的第一“异或”级、使用触发器632、634、636及638图解说明的最终数据寄存器级及使用“异或”门640图解说明的最终“异或”级以产生编码器输出642。
第一“异或”级门628及630分别接收输出信号624及来自触发器636及634的反馈信号。“异或”门628及630的输出分别被触发器632、634及636、638接收。触发器632、634、636及638受时钟信号clk的控制，其中触发器632及634在时钟信号的上升边缘处更新输出且触发器636及638在时钟信号的下降边缘处更新输出。
触发器634及636是其输出交叉耦合到第一“异或”级的“异或”门628及630的最终数据寄存器级的反馈触发器。在其它实施例中，分别从触发器638及632的输出提供到“异或”门628及630的反馈信号，其中触发器634及636从最终数据寄存器级中消除。然而，通过使用触发器634及636提供反馈信号到第一“异或”级来实现一更稳定设计。此减少然后仅需要被输入到同步化电路626的最终“异或”级中的触发器632及638的输出的任何额外例程。
同步化电路626的最终“异或”级包含单个“异或”门640，所述“异或”门640接收触发器632及638的输出且输出编码器输出642。编码器输出642是具有低输出偏斜的无假信号输出。
应注意，在串行编码器600中，单个逻辑层分离最终数据寄存器级与编码器输出。因此，贡献编码器输出的信号的个别偏斜保持为极低。此外，应注意，仅来自最终数据寄存器级的两个信号(触发器632及638的输出)贡献编码器输出642，此进一步减少输出偏斜。减少从最终寄存器级到编码器输出的路径数目还简化输出偏斜分析。
图8是图解说明根据本发明其它实施例的MDDI串行编码器800的电路图。MDDI串行编码器800在数个方面类似于图6的MDDI串行编码器600，但其采用不同的同步化电路实施方案812。应注意，实际上，同步化电路等效于双边缘触发器且因此，双边缘触发器或功能等效电路的任何实施方案可用于根据本发明实施例的同步化电路。
在图8中，同步化电路812包含使用触发器804及806图解说明的最终数据寄存器级及多路复用器808。触发器804及806接收多路复用器622的输出信号624且受时钟信号802控制，其中触发器804在时钟信号802的上升边缘处更新其输出且触发器806在时钟信号802的下降边缘处更新其输出。触发器804及806的输出随后形成到多路复用器808的输入。多路复用器808也受时钟信号802控制，其中当时钟信号802为高时，触发器804的输出从多路复用器808被输出且当时钟信号802为低时，触发器806的输出从多路复用器808被输出以产生编码器输出810。注意，在实施例800中，编码器输出810具有关于时钟信号802的竞争状态。此竞争状态是时钟信号802中的上升或下降边缘致使当前选定的到多路复用器808的输入改变的结果。只有在当前输入改变之前时钟信号802的上升或下降边缘已选择多路复用器808的其它输入作为编码器输出810的情况下，编码器输出810才是无假信号的。作为一实例，当时钟信号802为低时，触发器806的输出作为编码器输出810从多路复用器808输出。在时钟信号802的上升边缘处，触发器806的输出将更新为新的状态而同时触发器804的输出被选择为作为编码器输出810的多路复用器808的输出。为避免编码器输出810上的假信号，时钟信号802通过多路复用器808到达编码器输出810的延迟必须小于时钟信号802通过触发器804或806到达多路复用器808的延迟。只要满足此定时条件，则编码器输出810便为具有低输出偏斜的无假信号输出。
还应注意，在串行编码器800中，单个逻辑层将最终数据寄存器级与编码器输出分离，其中仅来自最终数据寄存器级的两个信号贡献编码器输出810，由此导致输出偏斜减少且输出偏斜分析得到简化。
实例定时图
图7是与图6中的MDDI串行编码器600的信号相关的实例定时图。在此实例图中，图7中被图解说明为信号sel[2:0]的选择输入过渡是根据具有无假信号多路复用器的MDDI编码器通常所需要的格雷码序列。因此，图6的多路复用器622与无假信号多路复用器相同操作，但没有无假信号输出要求。应注意，图7中的选择输入序列是实例性序列且还可使用其它选择输入序列。
图7中的信号din[7:0]对应于图6中的数据输入信号610。在图7中提供信号din[7:0]的实例性序列。
信号din_reg[7:0]对应于图6中所图解说明的信号din_reg[7:0]，且可根据图7中的信号data_en从信号din[7:0]产生。图7中提供信号din_reg[7:0]的实例性序列。
信号desired_data_out对应于图6中的信号624。
信号out_rise及out_fall分别对应于触发器632及638的输出。应注意out_rise＝(desired_data_out异或out_fall)且out_fall＝(desired_data_out异或out_rise)。还应注意，信号dout＝out_rise异或out_fall。因此，两个最终输出寄存器中的任一者均可通过保持或反相其输出来驱动desired_data_out值到dout。信号dout等效于信号desired_data_out但被延迟1/2个时钟循环。
图9是与图8中的MDDI串行编码器800的信号相关的实例定时图。类似于图7中的实例定时图，在图9中被图解说明为sel[2:0]的选择输入过渡是根据具有无假信号多路复用器的MDDI编码器通常所需的格雷码序列。然而，应注意，图9中所图解说明的选择输入序列仅是实例性且还可使用其它选择输入序列。
图9中的信号din[7:0]对应于图8中的数据输入信号610。图9中提供信号din[7:0]的实例性序列。
信号din_reg[7:0]对应于图8中触发器620的输出。图9中提供信号din_reg[7:0]的实例性序列。
信号desired_data_out对应于图8中的信号624。
信号pos_reg及neg_reg分别对应于图8中触发器804及806的输出。
信号dout对应于图8中的编码器输出dout 810。应注意，dout等效于desired_data_out信号，但被延迟1个时钟循环，其中1/2时钟循环延迟是由于触发器804及806所致且1/2时钟循环延迟是由于多路复用器808所致。
结论
尽管上文已描述本发明的各种实施例，但应了解，其均仅以举例而非限定的方式来呈现。所属技术领域的技术人员将明了，可在形式及细节上对其作出各种变化，此并不背离本发明的精神及范围。因此，本发明的广度和范围不应受限于上文所说明的任一实例性实施例，而应仅根据所附权利要求书及其等效内容来界定。

Claims (18)

1.一种串行编码器，其包括：
多路复用器，其具有多个数据输入、多个选择输入及一输出；
多个数据输入触发器，其耦合到所述多路复用器的所述数据输入；
多个选择输入触发器，其耦合到所述多路复用器的所述选择输入；及
同步化电路，其耦合到所述多路复用器的所述输出且提供所述串行编码器的输出，其中所述同步化电路包括最终数据寄存器级，所述最终数据寄存器通过单个逻辑层而与所述串行编码器的所述输出分离，由此导致所述编码器的低输出偏斜，从而使得所述同步化电路从所述多路复用器的所述输出中消除任何输出假信号。
2.如权利要求1所述的编码器，其中所述多路复用器具有八个数据输入及三个选择输入。
3.如权利要求1所述的编码器，其中所述多路复用器为非无假信号多路复用器。
4.如权利要求1所述的编码器，其中所述数据输入触发器及所述选择输入触发器均为D触发器。
5.如权利要求1所述的编码器，其中所述多路复用器的所述选择输入由计数器根据时钟信号来提供。
6.如权利要求5所述的编码器，其中所述多路复用器在所述时钟信号的每一边缘处输出一位。
7.如权利要求1所述的编码器，其中所述最终数据寄存器级为时钟驱动。
8.如权利要求1所述的编码器，其中所述串行编码器的所述输出完全由来自所述同步化电路的所述最终数据寄存器级的两个信号确定，由此导致所述编码器的低输出偏斜。
9.如权利要求1所述的编码器，其中所述编码器接收并行数据输入且将所述数据输入串行地输出到串行通信链路上。
10.如权利要求9所述的编码器，其中所述串行通信链路为移动显示数字接口(MDDI)链路。
11.如权利要求1所述的编码器，其中所述同步化电路是使用任何双边缘触发器来实施。
12.一种串行编码器，其包括：
用于存储多个数据输入位的装置；
用于存储多个选择输入位的装置；
用于根据所述多个选择输入位所产生的输入选择序列串行地输出所述多个数据输入位的装置；及
用于从所述串行输出装置的输出中消除假信号由此产生无假信号的串行编码器输出的装置，其中用于消除所述假信号的装置包含时钟驱动寄存器级，所述寄存器级通过单个逻辑层而与所述串行编码器输出分离，由此导致所述编码器的低输出偏斜。
13.如权利要求12所述的串行编码器，其中所述用于消除假信号的装置包含同步化电路。
14.如权利要求12所述的串行编码器，其中所述串行输出装置在时钟信号的每一边缘处输出一位，由此使得所述串行编码器成为双倍数据速率编码器。
15.如权利要求12所述的串行编码器，其中所述串行编码器输出完全由来自所述寄存器级的两个信号确定，由此导致所述编码器的低输出偏斜。
16.如权利要求12所述的串行编码器，其中所述编码器接收并行数据输入且将所述数据输入串行地输出到串行通信链路上。
17.如权利要求16所述的串行编码器，其中所述串行通信链路为移动显示数字接口(MDDI)链路。
18.如权利要求12所述的串行编码器，其中所述用于消除假信号的装置包含双边缘触发器。
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