DE69730775D1 - Logische Schaltung und zugehöriges Herstellungsverfahren - Google Patents

Logische Schaltung und zugehöriges Herstellungsverfahren

Info

Publication number
DE69730775D1
DE69730775D1 DE69730775T DE69730775T DE69730775D1 DE 69730775 D1 DE69730775 D1 DE 69730775D1 DE 69730775 T DE69730775 T DE 69730775T DE 69730775 T DE69730775 T DE 69730775T DE 69730775 D1 DE69730775 D1 DE 69730775D1
Authority
DE
Germany
Prior art keywords
manufacturing process
logical circuit
associated manufacturing
logical
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69730775T
Other languages
English (en)
Other versions
DE69730775T2 (de
Inventor
Koji Fujii
Takakuni Douseki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP23130696A external-priority patent/JPH1065507A/ja
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE69730775D1 publication Critical patent/DE69730775D1/de
Application granted granted Critical
Publication of DE69730775T2 publication Critical patent/DE69730775T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/501Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
DE69730775T 1996-05-22 1997-05-21 Logische Schaltung und zugehöriges Herstellungsverfahren Expired - Lifetime DE69730775T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP15026896 1996-05-22
JP15026896 1996-05-22
JP23130696 1996-08-13
JP23130696A JPH1065507A (ja) 1996-08-13 1996-08-13 スイッチ回路および論理回路

Publications (2)

Publication Number Publication Date
DE69730775D1 true DE69730775D1 (de) 2004-10-28
DE69730775T2 DE69730775T2 (de) 2005-09-29

Family

ID=26479925

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69730775T Expired - Lifetime DE69730775T2 (de) 1996-05-22 1997-05-21 Logische Schaltung und zugehöriges Herstellungsverfahren

Country Status (3)

Country Link
US (2) US6111427A (de)
EP (1) EP0809362B1 (de)
DE (1) DE69730775T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0809362B1 (de) * 1996-05-22 2004-09-22 Nippon Telegraph And Telephone Corporation Logische Schaltung und zugehöriges Herstellungsverfahren
JP3777768B2 (ja) * 1997-12-26 2006-05-24 株式会社日立製作所 半導体集積回路装置およびセルライブラリを記憶した記憶媒体および半導体集積回路の設計方法
US6693331B2 (en) * 1999-11-18 2004-02-17 Intel Corporation Method of fabricating dual threshold voltage n-channel and p-channel MOSFETS with a single extra masked implant operation
JP3416628B2 (ja) * 2000-04-27 2003-06-16 松下電器産業株式会社 半導体集積回路装置
JP3523611B2 (ja) * 2000-05-31 2004-04-26 日本電信電話株式会社 差動型論理回路
JP3912960B2 (ja) * 2000-06-20 2007-05-09 株式会社東芝 半導体集積回路、論理演算回路およびフリップフロップ
US6369606B1 (en) * 2000-09-27 2002-04-09 International Business Machines Corporation Mixed threshold voltage CMOS logic device and method of manufacture therefor
JP3614125B2 (ja) * 2000-10-23 2005-01-26 三星電子株式会社 Cpフリップフロップ
US6918091B2 (en) * 2000-11-09 2005-07-12 Change Tools, Inc. User definable interface system, method and computer program product
US6668358B2 (en) * 2001-10-01 2003-12-23 International Business Machines Corporation Dual threshold gate array or standard cell power saving library circuits
US6586294B1 (en) 2002-01-02 2003-07-01 Intel Corporation Method of fabricating MOSFET transistors with multiple threshold voltages by halo compensation and masks
US6981231B2 (en) * 2002-02-22 2005-12-27 Hewlett-Packard Development Company, L.P. System and method to reduce leakage power in an electronic device
US6933744B2 (en) * 2002-06-11 2005-08-23 The Regents Of The University Of Michigan Low-leakage integrated circuits and dynamic logic circuits
US6849492B2 (en) * 2002-07-08 2005-02-01 Micron Technology, Inc. Method for forming standard voltage threshold and low voltage threshold MOSFET devices
JP3916536B2 (ja) * 2002-09-02 2007-05-16 沖電気工業株式会社 Lsiデバイスの製造方法
JP4736313B2 (ja) * 2002-09-10 2011-07-27 日本電気株式会社 薄膜半導体装置
US7451413B1 (en) * 2003-01-03 2008-11-11 Marvell International Ltd. Methods of minimizing leakage current by analyzing post layout information and associated threshold voltage and leakage current
US7188325B1 (en) * 2004-10-04 2007-03-06 Advanced Micro Devices, Inc. Method for selecting transistor threshold voltages in an integrated circuit
US20090108905A1 (en) * 2007-10-24 2009-04-30 National Chung Cheng University Dynamic NP-swappable body bias circuit
US8252649B2 (en) 2008-12-22 2012-08-28 Infineon Technologies Ag Methods of fabricating semiconductor devices and structures thereof
US8151224B1 (en) * 2008-12-29 2012-04-03 Altera Corporation Method of designing integrated circuits including providing an option to select a mask layer set
US10169500B2 (en) * 2011-08-08 2019-01-01 International Business Machines Corporation Critical path delay prediction
TWI637484B (zh) 2013-12-26 2018-10-01 日商半導體能源研究所股份有限公司 半導體裝置
JP2022022804A (ja) 2020-07-07 2022-02-07 キオクシア株式会社 半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4107548A (en) * 1976-03-05 1978-08-15 Hitachi, Ltd. Ratioless type MIS logic circuit
JPS5772429A (en) * 1980-10-22 1982-05-06 Toshiba Corp Semiconductor integrated circuit device
US4441039A (en) * 1981-11-20 1984-04-03 International Business Machines Corporation Input buffer circuit for semiconductor memory
US4714840A (en) * 1982-12-30 1987-12-22 Thomson Components - Mostek Corporation MOS transistor circuits having matched channel width and length dimensions
US4563599A (en) * 1983-03-28 1986-01-07 Motorola, Inc. Circuit for address transition detection
JPS6074817A (ja) * 1983-09-30 1985-04-27 Fujitsu Ltd 集積回路
JP2574742B2 (ja) * 1984-04-09 1997-01-22 三菱電機株式会社 半導体集積回路装置
JPH04263468A (ja) * 1991-02-19 1992-09-18 Fujitsu Ltd 半導体装置の製造方法
JP3184265B2 (ja) * 1991-10-17 2001-07-09 株式会社日立製作所 半導体集積回路装置およびその制御方法
US5486774A (en) * 1991-11-26 1996-01-23 Nippon Telegraph And Telephone Corporation CMOS logic circuits having low and high-threshold voltage transistors
KR0169157B1 (ko) * 1993-11-29 1999-02-01 기다오까 다까시 반도체 회로 및 mos-dram
JP3249293B2 (ja) * 1994-05-30 2002-01-21 富士通株式会社 半導体集積回路
US5594371A (en) * 1994-06-28 1997-01-14 Nippon Telegraph And Telephone Corporation Low voltage SOI (Silicon On Insulator) logic circuit
JP2689950B2 (ja) * 1995-04-13 1997-12-10 日本電気株式会社 高速低電力型デコード回路
US5821769A (en) * 1995-04-21 1998-10-13 Nippon Telegraph And Telephone Corporation Low voltage CMOS logic circuit with threshold voltage control
EP0809362B1 (de) * 1996-05-22 2004-09-22 Nippon Telegraph And Telephone Corporation Logische Schaltung und zugehöriges Herstellungsverfahren

Also Published As

Publication number Publication date
US6426261B1 (en) 2002-07-30
EP0809362B1 (de) 2004-09-22
EP0809362A3 (de) 1999-07-21
DE69730775T2 (de) 2005-09-29
US6111427A (en) 2000-08-29
EP0809362A2 (de) 1997-11-26

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