EP1244215B1 - Phase lock loop gain control using unit current sources - Google Patents
Phase lock loop gain control using unit current sources Download PDFInfo
- Publication number
- EP1244215B1 EP1244215B1 EP02252014A EP02252014A EP1244215B1 EP 1244215 B1 EP1244215 B1 EP 1244215B1 EP 02252014 A EP02252014 A EP 02252014A EP 02252014 A EP02252014 A EP 02252014A EP 1244215 B1 EP1244215 B1 EP 1244215B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- pll
- vco
- current
- gain
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
- H03B5/1215—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
- H03B5/1243—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising voltage variable capacitance diodes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
- H03B5/1246—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising transistors used to provide a variable capacitance
- H03B5/1253—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising transistors used to provide a variable capacitance the transistors being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/1262—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements
- H03B5/1265—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements switched capacitors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/1275—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator having further means for varying a parameter in dependence on the frequency
- H03B5/1278—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator having further means for varying a parameter in dependence on the frequency the parameter being an amplitude of a signal, e.g. maintaining a constant output amplitude over the frequency range
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
- H03D7/165—Multiple-frequency-changing at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/18—Modifications of frequency-changers for eliminating image frequencies
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
- H03J5/24—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with a number of separate pretuned tuning circuits or separate tuning elements selectively brought into circuit, e.g. for waveband selection or for television channel selection
- H03J5/242—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with a number of separate pretuned tuning circuits or separate tuning elements selectively brought into circuit, e.g. for waveband selection or for television channel selection used exclusively for band selection
- H03J5/244—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with a number of separate pretuned tuning circuits or separate tuning elements selectively brought into circuit, e.g. for waveband selection or for television channel selection used exclusively for band selection using electronic means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
- H03L7/0898—Details of the current generators the source or sink current values being variable
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1072—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the charge pump, e.g. changing the gain
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
- H03B2200/003—Circuit elements of oscillators
- H03B2200/0046—Circuit elements of oscillators including measures to switch the gain of an amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
- H03B2200/003—Circuit elements of oscillators
- H03B2200/0048—Circuit elements of oscillators including measures to switch the frequency band, e.g. by harmonic selection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
- H03B2200/003—Circuit elements of oscillators
- H03B2200/005—Circuit elements of oscillators including measures to switch a capacitor
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
- H03B2201/02—Varying the frequency of the oscillations by electronic means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
- H03B2201/02—Varying the frequency of the oscillations by electronic means
- H03B2201/0208—Varying the frequency of the oscillations by electronic means the means being an element with a variable capacitance, e.g. capacitance diode
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
- H03B2201/02—Varying the frequency of the oscillations by electronic means
- H03B2201/025—Varying the frequency of the oscillations by electronic means the means being an electronic switch for switching in or out oscillator elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J2200/00—Indexing scheme relating to tuning resonant circuits and selecting resonant circuits
- H03J2200/10—Tuning of a resonator by means of digitally controlled capacitor bank
Definitions
- the present invention generally relates to a gain compensator circuit, more specifically to phase lock loop gain control using scaled unit current sources, and to a method of compensating the gain of a phase lock loop.
- Radio frequency (RF) transmitters and receivers perform frequency translation by mixing an input signal with a local oscillator (LO) signal.
- the LO signal should have a frequency spectrum that is as close to a pure tone as possible in order to maximize system performance during the signal mixing operation.
- the deviation of the LO signal from a pure tone is quantified as phase noise or phase jitter, and is generally referred to as spectral purity. In other words, a LO signal with good spectral purity has low phase noise.
- Phase-locked loops are often used in frequency synthesizers to generate the LO signal.
- a PLL frequency synthesizer produces an output signal, typically a sinewave or square wave, that is a frequency multiple of an input reference signal.
- the PLL output signal is also in phase synchronization with the input reference signal.
- PLLs are feedback loops, and therefore are susceptible to instability. Therefore, loop stability is a key performance parameter for PLLs, in addition to spectral purity of the output signal.
- a resonant-tuned voltage controlled oscillator is typically utilized in a PLL to generate the PLL output signal.
- a resonant tuned VCO includes an active device and a resonant LC circuit, where the impedance of the resonant LC circuit becomes a short or an open at a resonant frequency.
- the resonant circuit is connected in parallel with the active device, a positive feedback path is created in the active device at the resonant frequency of the LC circuit. The positive feedback path causes the active device to oscillate at the resonant frequency of the LC circuit.
- the resonant tuned LC circuit typically includes multiple fixed capacitors that can be switched in or out of the LC circuit, a varactor diode, and at least one inductor.
- the resonant frequency of the LC circuit (and therefore the oscillation frequency of the VCO) is tuned via a coarse tuning mechanism and a fine tuning mechanism.
- Coarse frequency tuning (or band-selection) is performed by switching one or more of the fixed capacitors in the LC circuit.
- fine frequency tuning is performed by changing the voltage across the varactor diode, which produces a capacitance that varies depending on the applied tuning voltage. Both tuning mechanisms operate by changing the capacitance, and therefore the resonant frequency of the LC circuit.
- the varactor tuning range is slightly larger than one fixed capacitor, and therefore provides some overlap between the fixed capacitors.
- VCO gain is defined as the VCO frequency shift per unit change in the varactor tuning voltage.
- a problem with varactor-tuned VCOs is that the VCO gain verses fixed capacitance is variable. In other words, the VCO frequency shift verses tuning voltage is dependent on the fixed capacitance that is switched-in to the LC circuit.
- the variable VCO gain creates difficulties when designing a PLL because the entire PLL loop gain, bandwidth, and damping response varies with respect to the oscillator frequency. This in turn makes it difficult to optimize the output phase noise and reduces overall spectral purity. Therefore, it is desirable to compensate for the variable VCO gain, in order to maintain the overall PLL gain at a desired optimum value.
- EP-A-0 627 820 refers to a charge pump having a reference circuitry, multiple parallel paths, a mirror circuit, a sourcing circuitry, and a sinking circuitry.
- the described charge pump may be incorporated into a phase locked loop circuit, where constant stability parameters are desired.
- the gain compensator invention compensates for gain variation in a varactor-tuned VCO in order to maintain the overall PLL gain at a desired level over frequency.
- the VCO includes a LC circuit that has multiple fixed capacitors that are arranged in parallel with the varactor diode and the active portion of the VCO. The fixed capacitors are switched-in to the LC circuit by corresponding capacitor control signals.
- Coarse frequency tuning also called band-select tuning
- Fine frequency tuning is performed by adjusting the tuning voltage on the varactor diode, where the VCO gain is defined as the frequency shift per unit change in varactor tuning voltage.
- VCO gain varies with the fixed capacitance that is switched-in to the LC circuit, and therefore changes with band-select tuning of the VCO.
- the gain compensator compensates for the variable VCO gain by generating a reference charge pump current for the PLL based on information that is carried in the capacitor control signal. Therefore, the gain compensator is able to simultaneously adjust the charge pump current to maintain an overall flat PLL gain as fixed capacitors are incrementally added to (or subtracted from) the LC circuit.
- the gain compensator includes one or more cells that each correspond to a particular VCO that can be switched into the PLL at a given time.
- a VCO control signal selects a particular VCO for the PLL based on frequency, and also activates the appropriate cell.
- Each cell includes a plurality of unit current sources, where each unit current source substantially replicates (or copies) a predefined reference scale current.
- the unit current sources are arranged into one or more groups, where each group corresponds to a fixed capacitor in the LC circuit. Each group of unit current generates a portion of the total pump current when the corresponding capacitor is switched-in to the LC circuit. The number of unit current sources in each group is determined to compensate for the variable VCO gain that occurs when the corresponding fixed capacitor is switched-in to the LC circuit.
- Each group of unit current sources is activated by the same capacitor control signal that controls the corresponding fixed capacitor. Therefore, when a fixed capacitor is switched-in to the LC circuit, the corresponding group of unit current sources is simultaneously activated and switched-in to the cell to compensate for the variable VCO gain that is caused by the fixed capacitor.
- An advantage of the gain compensator invention is that the number of unit current sources that are activated for a corresponding fixed capacitor is arbitrary, but the current produced is linearly proportional to the reference scale current. In other words, there is no predefined relationship between the number of unit current sources in each group that would restrict the relative amount of current produced by each group. Therefore, the total pump current can be freely optimized to incrementally adjust for the variable VCO gain that is associated with various combinations of fixed capacitors.
- a further advantage of the gain compensator invention is that the reference scale current for the gain compensator cells is generated based on a PLL control signal.
- the PLL control signal specifics various PLL characteristics, such as the frequency of the reference signal, the PLL bandwidth, and the PLL damping factor, etc. Since the unit current sources are configured to replicate the reference scale current, all of the unit current sources can be simultaneously adjusted by changing the reference scale current. Therefore, the charge pump current can be efficiently adjusted to tune the mentioned characteristics of PLL for different operating conditions, without requiring the replacement of PLL components.
- FIG. 1A illustrates a tuner 100 that is an example tuner environment for the present invention
- FIG. 1B illustrates dual frequency conversion that is performed by the tuner 100
- FIG. 2 illustrates a PLL 200 that can be used with the tuner 100
- FIG. 3 illustrates a VCO 300 that can be used with the PLL 200
- FIG. 4 illustrates variable VCO gain
- FIG. 5 illustrates a PLL 500 that includes a gain compensator 502, according to embodiments of the present invention
- FIG. 6 illustrates a ROMDAC 600 that is one embodiment of a gain compensator, according to embodiments of the present invention
- FIG. 7 illustrates a ROMDAC 700 having an expanded look-up table 701, according to embodiments of the present invention
- FIG. 8 illustrates a gain compensator 800 having a current scaler 804 that forms a current mirror configuration with one or more gain compensator cells 806, according to embodiments of the present invention
- FIG. 9 illustrates a gain compensator cell 806 having multiple unit current sources, according to embodiments of the present invention.
- FIG. 10 illustrates the current scaler 804, according to embodiments of the present invention.
- FIG. 11 illustrates a flowchart 1100 that describes the operation of a PLL having compensation for nonlinear VCO gain, according to embodiments of the present invention.
- FIG. 12 illustrates a flowchart 1200 that describes the operation of a gain compensator cell, according to embodiments of the present invention.
- FIG. 1A illustrates a schematic of a tuner assembly 100 that has an RF automatic gain control circuit (AGC) 102, and a tuner 134.
- the tuner assembly 100 receives an RF input signal 101 having multiple channels and down-converts a selected channel to an IF frequency, to produce an IF signal 133.
- the RF input signal 101 can include multiple TV channels that typically have 6 MHZ frequency spacings and cover a range of 57-860 MHZ, and where the selected channel is down-converted to an IF frequency at 44 MHZ, 36 MHZ or some other desired IF frequency for further processing.
- the structure and operation of the AGC circuit 102 and the tuner 134 are described in further detail below.
- the AGC circuit 102 provides automatic gain control using a variable resistor 104 and a low noise amplifier (LNA) 106.
- the variable resistor 104 attenuates the RF input signal 101 according to a control signal 103.
- the control signal 103 is based on the signal amplitude of the IF signal 133 so that the RF front-end gain can be adjusted to achieve a desired amplitude for the IF signal 133.
- the LNA 106 provides low noise amplification and converts a single-ended input signal to a differential RF signal 107.
- the tuner 134 has a dual conversion architecture (one up-conversion, one down-conversion) that includes an input mixer 108 and an image reject mixer 118.
- the input mixer 108 is driven by a first phase locked loop (PLL) 110 that has coarse tuning capability from 1270-2080 MHz.
- the image reject mixer 118 has two component mixers 120a and 120b that are driven in quadrature by a second PLL 124 through a quadrature polyphase filter 122.
- the PLL 124 has a relatively fixed frequency of 1176 MHZ (for a 44 MHZ IF) and has fine frequency tuning capability.
- a polyphase filter 126 is coupled to the output of the image reject mixer 118 to combine the quadrature outputs of the mixers 120.
- Two separate off-chip surface acoustic wave (SAW) filters 114 and 130 are used to perform IF filtering in the tuner 134.
- the first SAW filter 114 is connected between the first mixer 108 and the image reject mixer 118.
- the passband of the SAW filter 114 is centered at 1220 MHZ, and is only a few channels wide (e.g. 1-3 channels wide or 18 MHZ for 6 MHZ TV channel spacings).
- the second SAW filter 130 has a passband at 44 MHZ and is coupled to the output of the polyphase filter 126.
- various on-chip amplifiers 108, 116, 128, and 132 are included throughout the tuner 134 to provide signal amplification, as necessary.
- the operation of the tuner 134 is described as follows and in reference to the frequency spectrum that is illustrated in FIG.1B.
- the first mixer 108 mixes the RF signal 107 with a LO signal 109 that is generated by the PLL 110. Since the PLL 110 is tunable from 1270-2080 MHZ, the RF signal 107 is up-converted to a first IF 111 having a frequency that is above the 57-860 MHZ input frequency band.
- the first IF 111 is sent off-chip to the SAW filter 114, which has a narrow passband window centered at 1220 MHz.
- the first SAW filter 114 selects a desired channel 115 that is within its narrow passband window, and substantially rejects all of the remaining channels.
- a particular channel is selected by varying the frequency of the LO signal 109 so that the desired channel is up-converted into the narrow passband of the IF filter 114.
- the desired channel 115 (at 1220 MHZ) is sent back on-chip to the image reject mixer 118 that is driven by a quadrature LO signal 119 from the polyphase filter 122.
- the image reject mixer 118 down-converts the desired channel 115 to a 44 MHZ IF signal 127 that appears at the output of the polyphase filter 126, where I and Q components of the IF signal 127 are combined in the polyphase filter 126.
- the IF signal 127 is filtered a second time by the bandpass SAW filter 130 to reject any unwanted frequency harmonics, producing the output IF signal 133 at 44 MHZ and carrying the information in the desired channel.
- the first PLL 110 and the second PLL 124 are represented by the PLL 200 that is illustrated in FIG. 2.
- the PLL 200 generates a PLL output signal 227 that is a frequency multiple of a reference signal 201, and where the output signal 227 is phase-locked to the reference signal 201.
- the PLL 200 self-corrects for any phase (and therefore frequency) variations between the reference signal 201 and the output signal 227 via a feedback mechanism that is described as follows.
- the structure and operation of the PLL 200 are described as follows.
- the PLL 200 structure includes: a phase detector 202, a charge pump 204, a frequency divider 206, a loop filter 208, a coarse tuning circuit 214, a VCO assembly 222, and a LC resonant circuit 228.
- the loop filter 208 includes a variable resistor 210 and a variable capacitor 212 that are controlled by an I 2 C signal 207.
- the coarse tuning circuit 214 includes a comparator 216 and a shift register 218.
- the VCO assembly 222 includes multiple component VCOs 226a-c, where each VCO 226 preferably covers a particular frequency band. A VCO 226 is switched-in to the PLL 200 by closing a corresponding switch 224.
- the switches 224a-c are controlled by corresponding control signals 223a-c that make-up a VCO control bus 220.
- the LC resonant circuit 228 is connected in parallel with the VCO assembly 222 and includes: multiple fixed capacitors 232an having corresponding switches 230a-n, a varactor 234, and an inductor 236. One or more of the fixed capacitors 232 are switched in-parallel with the selected VCO 226 by closing the corresponding switch(s) 230.
- the switches 230 are controlled by corresponding control signals 239a-n that make-up a capacitor control bus 238.
- Each VCO 226 is a resonant tuned oscillator whose oscillation frequency is controlled by the resonant frequency of the parallel LC circuit 228.
- coarse frequency tuning e.g. band-selection
- fine frequency tuning is performed by changing the control voltage on the varactor 234, which has a variable capacitance that changes with applied voltage.
- the VCO gain is defined as the change in the VCO output frequency per unit change in the voltage across the varactor 234.
- the PLL 200 operates based on known PLL feedback principles.
- a VCO 226 is selected based on the desired frequency of operation for the PLL 200, and is switched-in to the PLL 200 by closing the appropriate switch 224 using the appropriate control signal 223.
- the PLL output signal 227 from the selected VCO 226 is fed back to a phase detector 202 through the frequency divider 206.
- the frequency divider 206 normalizes the frequency of the output signal 227 to that of the reference signal 201 for comparison in the phase detector 202.
- the phase detector 202 compares the phase of the output signal 227 to the reference signal 201, and generates a DC error signal 203 that represents the phase difference between the two signals.
- the charge pump 204 receives the error signal 203 and a reference pump current 205.
- the charge pump 204 sources (or sinks) a percentage of the pump current 205 based on the error signal 203, as will be understood by those skilled in the arts.
- the output current of the charge pump 204 drives the loop filter 208 to produce a tuning voltage 209. Part of the tuning voltage 209 is dropped across the variable capacitor 212 to generate a tuning voltage 211.
- the tuning voltages 209 and 211 control the oscillation frequency of the selected VCO 226.
- the tuning voltages 209 and 211 adjust the resonant frequency of the LC circuit 228 (and therefore the oscillation frequency of the selected VCO 226) via a coarse tuning mechanism and a fine tuning mechanism, respectively. More specifically, the coarse tuning circuit 214 adds (or subtracts) one or more of the fixed capacitors 232a-n to the LC circuit 228 based on the tuning voltage 211. Similarly, the tuning voltage 209 directly adjusts the voltage (and therefore the capacitance) of the varactor 234 to implement fine frequency tuning. Both tuning mechanisms adjust the oscillation frequency of the VCO 226 by changing the capacitance of the LC circuit 228, which shifts the resonant frequency of the LC circuit 228. The tuning range of the varactor 234 is slightly larger than one fixed capacitor 232, and therefore provides some tuning overlap between the fixed capacitors 232.
- the coarse tuning circuit 214 is described further below.
- the coarse tuning circuit 214 includes a window comparator 216 and a bi-directional shift register 218.
- the window comparator 216 receives the tuning voltage 211 and also receives input reference voltages v 1 and v 2 .
- the window comparator 216 determines if the voltage 211 is within a voltage "window" that is defined between the input references voltages v 1 and v 2 , and generates a control signal 217 that controls the bi-directional shift register 218 based on this determination.
- the shift register 218 stores a series of bits that control the capacitor switches 230 via the control bus 238 to add (or subtract) the corresponding capacitors 232 to (or from) the LC circuit 228.
- a "1" bit on the control line 239 causes the corresponding switch 230 to close and thereby adds the corresponding capacitor 232 to the LC circuit 228.
- a "0" bit on the control line 239 causes the switch 230 to open and thereby subtracts the corresponding capacitor 232 from the LC circuit 228.
- the coarse tuning circuit 214 operates to self-correct coarse variations in the oscillation frequency of the selected VCO 226 by adding or subtracting capacitors 232, based on the tuning voltage 211. If the comparator 216 determines that the voltage 211 is below v 1 , then the comparator 216 causes a series of "1"s to be shifted through the shift register 218, which incrementally adds capacitors 232 to the LC circuit 228 until the tuning voltage 211 is within the v 1 -to-v 2 voltage window.
- the comparator 216 determines that the voltage 211 is above the voltage v 2 , then the comparator 216 causes a series of "0"s to be shifted through the shift register 218, which incrementally subtracts capacitors 232 from the LC circuit 228 until the tuning voltage 211 is within the v 1 -to-v 2 voltage window. As described above, the frequency of the selected oscillator 226 changes whenever capacitance is added to, or subtracted from, the LC circuit 228. If the comparator 216 determines that the voltage 211 is within the voltage window defined by v 1 and v 2 , then no action is taken and the fixed capacitance in the LC circuit 228 remains unchanged.
- the tuning voltage 211 is within an acceptable voltage range (or “window"), and correspondingly, the frequency of the output signal 227 is within an acceptable frequency range. Therefore the number of the fixed capacitors 232 that are switched-in to the LC circuit 228 is not changed.
- FIG. 3 illustrates a differential VCO 300 as one embodiment of VCO 226 and the LC resonant circuit 228.
- the VCO 300 is meant for example purposes only and is not meant to limit the invention in any way.
- Other oscillator configurations could be utilized to practice the invention, as will be understood by those skilled in the relevant arts based on the discussions given herein.
- the VCO 300 includes the active VCO portion 226 and the resonant LC circuit 228.
- the active portion includes a pair of cross coupled transistors 302a and 302b that oscillate at the resonant frequency of LC circuit 228.
- the drain of transistor 302a is connected to the gate of transistor 302b.
- the drain of transistor 302b is connected to the gate of the transistor 302a.
- the LC circuit 228 is also coupled to the drains of the transistors 302. At resonance, the LC circuit 228 causes a positive feedback path between the cross-coupled transistors 302, which causes the transistors to oscillate at the resonant frequency of the LC circuit 228, producing the differential output signal 227.
- the oscillation frequency of the VCO 300 can be tuned by two mechanisms. Coarse frequency tuning (or band selection) is performed by adding or subtracting the fixed capacitors 232 using the corresponding switches 230. Fine frequency tuning is performed by the tuning voltage 209, which varies the capacitance produced by the series-connected varactor diodes 234a and 234b that are attached to the drains of the transistors 302. The frequency change of VCO 300 per unit change in varactor 234 voltage is defined as the VCO gain. As stated above, the tuning range of the varactor 234 is slightly larger than the capacitance of one fixed capacitor 232, and therefore provides some tuning overlap between the fixed capacitors 232.
- the varactors 234 are PN junction varactors, and in an alternate embodiment these varactors 234 are MOSFET varactors, depending on the designer's preference.
- PLL gain is defined as the frequency change of the output signal verses the phase difference between the feedback signal and the reference signal.
- the feedback PLL gain H(s) 1/N, where N is the feedback frequency division ratio.
- the overall open loop gain is G(s)H(s)
- the overall closed-loop gain is G(s)/[1+G(s)H(s)].
- the PLL 200 performs coarse frequency tuning by incrementally adding (or subtracting) one or more of the fixed capacitors 232 that are in-parallel with the selected VCO 226. Fine frequency tuning is performed by adjusting the voltage on the varactor 234, where the VCO gain is defined as the frequency shift per unit change in the tuning voltage 209.
- a problem with varactor-tuned VCOs is that the VCO gain verses the fixed capacitance 232 is variable.
- FIG.4 illustrates this characteristic with a graph of VCO gain 402 verses fixed capacitance. As shown, the VCO gain curve 402 is reduced for a large fixed capacitance and is increased for a small fixed capacitance. Variable VCO gain is undesirable because it causes the PLL forward gain to change according to Eq. 2.
- this VCO gain variability can cause loop instability, and reduced spectral purity in the PLL output signal.
- the VCO gain variability is compensated for by a compensator gain 404 so that the overall PLL gain 406 remains relatively flat for variations in fixed capacitance (and therefore VCO frequency). More specifically, the charge pump current 205 is compensated to counter the variable VCO gain so that the overall PLL gain is flat.
- FIG. 5 illustrates a PLL 500 that has a gain compensator 502 to adjust the charge pump current 205 in order to linearize (and flatten) the overall PLL gain of the PLL 500.
- the gain compensator 502 generates the pump current 205 based on the control information carried by the VCO control bus 220 and the capacitor control bus 238.
- the VCO control bus 220 selects the appropriate VCO 226 based on the desired frequency range for the PLL output signal 227.
- the capacitor control bus 238 selects the fixed capacitors 232 that are switched-in parallel with the selected VCO 226 for coarse frequency tuning of the VCO 226. Therefore, the gain compensator 502 can tailor the reference pump current 205 for a specified VCO 226 at a specified fixed capacitance 232 value, and thereby compensate for the variable VCO gain vs. fixed capacitance.
- FIG 6 illustrates a read only memory digital-to-analog converter (ROMDAC) 600 that is one example embodiment of the gain compensator 502, according to embodiments of the invention.
- the ROMDAC 600 includes a look-up table 602 and a current digital-to-analog converter 610.
- the lookup table 602 stores pump current values 604a-n that are indexed by the selected VCO 226 and a fixed capacitance total 606, where the fixed capacitance total 606 is the parallel sum of the capacitors 232 that are switched-in to the LC circuit 228.
- the pump current values 604 are selected to compensate for the variable VCO gain vs. capacitance, given an identified VCO 226 and the fixed capacitance total 606.
- the PLL 200 is characterized beforehand for each VCO 226 to determine the pump current values 604 that produces a flat overall PLL gain for various capacitance totals 606.
- the look-up table 602 outputs a pump current value 608 that corresponds to identified VCO 226 and the fixed capacitance total 606.
- the DAC 610 converts the pump current value 608 to the actual analog pump current 205 that drives the charge pump 204.
- the lookup table 602 selects the appropriate pump current value 604 so as to maintain a flat overall PLL gain. Therefore, the pump current 205 is adjusted for various total capacitance 606 to counteract the variable gain of the selected VCO 226, and thereby flatten the overall gain of the PLL 500.
- the pump current values 604 can be totally arbitrary and mathematically unrelated to each other.
- the pump currents 604 can be individually selected to produce an optimum overall PLL gain for a given VCO 226 and capacitance total 606, without being restricted by any mathematical relationship.
- the various pump currents 604 are mathematically related to each other, or to the VCO control signal 220 or the capacitor control signal 238.
- PLL loop gain In addition to PLL gain, it is desirable to tune various other PLL characteristics, such input reference frequency, loop bandwidth, damping factor, etc. This allows the same PLL to be used in different operating environments. For instance, it is often desirable to have a PLL configuration that is operable with a number of different reference frequencies. If the frequency of the reference signal 201 increases by factor of two, the PLL loop gain should preferably be adjusted to compensate for this increase so that the PLL loop remains stable and accurate. The PLL loop gain can be appropriately adjusted by reducing the frequency division of the frequency divider 206 by a factor of two. However, this would require replacement of the frequency divider 206 for each possible reference frequency, or the use of a programable frequency divider. Alternatively, the charge pump current could be reduced by a factor of two to get the same effect.
- FIG. 7 illustrates a ROMDAC 700 as another embodiment of the gain compensator 502, according to embodiments of the present invention.
- the ROMDAC 700 has an expanded lookup table 701 that has multiple sets 710a-d of pump current values, where the sets 710 tune various PLL characteristics in addition to compensating for variable VCO gain.
- Some PLL characteristics include, but are not limited to, PLL reference signal frequency, loop bandwidth, loop damping, etc.
- sets 710a and 710b have pump current values 702a-n and 704a-n, respectively, which are customized for different reference frequencies.
- the pump current values 702a-n can correspond to a first reference signal 201 frequency
- the pump current values 704a-n can correspond to a second reference signal 201 frequency.
- the pump current value 608 can be selected from the appropriate pump current set 710.
- the pump current sets 710c and 710d are customized to maintain loop bandwidth for different loop damping factors.
- the loop damping factor is increased or decreased by adjusting the variable resistor 210 in the loop filter 208, which also determines the loop bandwidth. If the damping factor is changed, then the loop bandwidth can be held constant by selecting the appropriate set 710c or 710d that adjusts the charge pump current 205 to sufficiently counter the effect on the loop bandwidth.
- multiple PLL characteristics can be adjusted or tuned in addition to PLL gain. This allows the same PLL 500 to be used under different PLL operating conditions, without replacing PLL components.
- the number of pump current sets 710 can be expanded to adjust any number of PLL characteristics, assuming there is sufficient memory space in the look-up table 701.
- FIG. 8 illustrates a gain compensator 800 that is another embodiment of the gain compensator 502 in FIG. 5.
- the gain compensator 800 includes: a voltage generator 801, gain compensator cells 806a-c that correspond to VCOs 226a-c, and PFETs 808a-c that correspond to the gain compensator cells 806a-c.
- Each gain compensator cell 806 generates a prospective pump current 807 that compensates for the variable VCO gain of its corresponding VCO 226 caused by the fixed capacitors 232. Since only one VCO 226 is operational at a given time, only one prospective pump current 807 becomes the actual pump current 205 that feeds the charge pump 204.
- the PFETs 808 operate as switches that are controlled by the VCO control signals 239 and select the appropriate prospective pump current 807 to correspond with the selected VCO 226. For example, if the VCO 226a is the selected VCO 226, then the control signal 239a causes the PFET 808a to conduct so that the current 807a becomes the feed for the pump current 205. Accordingly, control signals 239b and 239c cutoff their respective PFETs 808b and 808c, and therefore only the current 807a feeds the pump current 205.
- the structure of the gain compensator cell 806 is shown in FIG 9 and includes: switches 902a-d that are controlled by the respective capacitor control signals 239a-d, and unit current sources 906a-j that are arranged in groups 904a-d.
- each unit current source 906 generates substantially the same amount of unit current (within transistor tolerances), where the amount of unit current is based on a gate voltage 805 that is generated by the voltage generate 801.
- Each group 904 corresponds to a capacitor 232, and generates a portion of the total pump current 205 when the respective capacitor 232 is switched-in to the LC circuit 228.
- the number of unit current sources 906 in each group 904 is selected to compensate for the variable VCO gain that occurs when the corresponding capacitor 232 is switched-in to the LC circuit 228.
- group 904a corresponds to capacitor 232a, and has 4 unit current sources 906 to compensate for variable VCO gain that is caused by the capacitor 232a.
- group 904b only has 2 unit current sources 906 to address the variable VCO gain caused by the capacitor 232b, and so on.
- the number of current sources 4,2,3,1 that are shown in FIG. 9 for the groups 902a-d are for illustration purposes only, and is not meant to be limiting.
- the number of groups 904, namely 4 as shown is not meant to be limiting. In embodiments of the invention, the number of groups 904 should be less than or equal to the number of fixed capacitors 232.
- a group 904 is switched into the gain compensator cell 806 when the corresponding switch 902 connects Vg 805 to the unit current sources 906 in the group 904.
- the Vg 805 activates the current sources 906 and determines the current produced by each current source 906.
- the switches 902 are controlled by the same capacitor control signals 239 that switches-in the respective capacitors 232 into the LC circuit 228. Therefore, when a capacitor 232 is switched-in to the LC circuit 228, the corresponding group 904 will be switched-in to the gain compensator cell 806, and therefore contribute to the prospective pump current 807.
- the charge pump current 205 is simultaneously adjusted to maintain a flat overall PLL as the capacitors 232 are incrementally added to (or subtracted from) the LC circuit 228.
- Each unit current source 906 is preferably a PFET transistor, as shown.
- other transistor devices and configurations could be used for the unit current sources 906, including N-FET transistors, as will be understood by those skilled in the relevant arts based on the discussions given herein. These other transistor devices and configurations are within the scope and spirit of the present invention. For example, simultaneous use of NFET and PFET current sources would permit the gain compensator to compensate for a non-monotonic VCO gain verses fixed capacitance characteristic.
- the voltage generator 801 and the current sources 906 operate as a "current mirror", where the drain currents of the selected unit current sources 906 copy or "mirror” a reference scale current 812. More specifically, the current scaler 804 sets the reference scale current 812, which operates as a current sink for the PFET 802.
- the PFET 802 operates as a diode because the gate and drain of the PFET 802 are shorted together by a conductor 813.
- the drain current 814 of the PFET 802 is substantially the same as the reference scale current 812 because there is substantially zero current on the conductor 813.
- the diode-connected PFET 802 generates the gate voltage 805 at its gate terminal to correspond with the drain current 814, and therefore to the reference scale current 812.
- the gate voltage 805 is applied to the gate of the current sources 906 when their respective group 904 is selected by the capacitor control signals 239.
- the current sources 906 will reproduce (or "mirror") the drain current 814 due to the common gate voltage 805, if the device characteristics of the current sources 906 are sufficiently similar to those of the PFET 802. This current mirror effect occurs because two or more FETs that have a common gate-to-source voltage and similar device characteristics will generate substantially the same drain current.
- the PFET 802 and the current sources 906 are fabricated on the same semiconductor wafer using the same process, which improves the commonality of device characteristics.
- the unit current sources 906 will generate a current that is proportional to the scale factor, as will be understood by those skilled in the relevant arts. This increases the flexibility of the gain compensator cell 806, as the current sources 906 can be scaled relative to the PFET 802 as well as relative to each other.
- the current scaler 804 sets the reference scale current 812 based on a PLL control signal 810, where the PLL control signal 810 dictates various PLL characteristics such as the frequency of the reference signal 201, the PLL loop bandwidth, and PLL loop damping, etc.
- FIG. 10 illustrates one embodiment of the current scaler 804 and includes weighted current sources 1002a-n.
- the weighted current sources 1002a-n sink currents 1004a-n based the PLL variables in the PLL control signal 810.
- the current source 1002a can be adapted to generate a current 1004a that is proportional to the frequency of the reference signal 201
- the current source 1002b can be adapted to generate a current 1004b that is proportional to the desired loop bandwidth, etc.
- the currents 1004a-n are summed together to form the reference scale current 812 that feeds the diode-connected PFET 802. Therefore, changes in the PLL variables are reflected in the reference scale current 812, and ultimately in the drain currents of the unit current sources 906 because of the current mirror effect described herein. More specifically, the PFET drain current 814 is substantially the same as the reference scale current 812, and gets copied to the drain currents of the unit current sources 906.
- An advantage of using the current scaler 800 is that all of the current sources 906 (that are in a selected group 904) are simultaneously adjusted for changing PLL characteristics, in addition to compensating for variable VCO gain. Therefore, the prospective pump current 807 (and ultimately the final pump current 205) can be efficiently tuned to compensate for changing PLL characteristics. This allows the same PLL to be utilized under different operating conditions. Furthermore, the current scaler 804 reduces the size of the overall gain compensator because multiple sets of current sources 906 are not needed to address changing PLL characteristics. In contrast, the ROMDAC 700 requires multiple sets 710 of current values to address changing PLL characteristics, which increases the size of the ROMDAC 700.
- the frequency of the reference signal 201 increases by a factor of two, but the frequency divider 206 ratio is to remain constant.
- the same the frequency divider 206 can be used in the PLL 500 if the charge pump current 205 is reduced by approximately a factor of two. This is accomplished by reducing the reference scale current 812 that is generated by the current scaler 804, causing a corresponding reduction in the gate voltage 805.
- the current produced by the selected current sources 906 will be proportionally reduced by a factor of two. Therefore, the prospective current 807 (and the pump 205) will also be reduced by a factor of two as desired, and the same PLL 500 can be reused for the new reference frequency.
- the PLL damping factor ⁇ is to be increased, but the PLL bandwidth is to be held constant.
- the PLL damping factor ⁇ is increased by increasing the resistance of the variable resistor 210 in the loop filter 208.
- this also changes the loop bandwidth as will be understood by those skilled in the arts.
- the current scaler 804 adjusts the reference scale current 812, and therefore the unit current sources 906 to produce a reference pump current 205 that compensates for the loop bandwidth.
- the gain compensator 800 is able to compensate for variable VCO gain and simultaneously tune other PLL characteristics by using the current mirror configuration described herein.
- These other PLL characteristics include but are not limited to changes in reference frequency, damping factor, and bandwidth.
- the flowchart 1100 further describes the operation of the gain compensator 800 and VCO gain compensation according to embodiments of the present invention.
- the order of the steps in the flowchart 1100 is not limiting as all or some of the steps can be performed simultaneously or in a different order, as will be understood by those skilled in the arts.
- a VCO 226 is selected from the VCO 226a-c based on the desired frequency of the output signal 227. The selection is made by closing the appropriate switch 230 using the control signals 239 to switch-in the desired VCO 226.
- step 1104 the VCO output signal 227 is fed back to the phase detector 202 through a frequency divider 206.
- the frequency divider 206 normalizes the frequency of the output signal 227 to that of the reference signal 201 for comparison in the phase detector 202.
- step 1106 the phase detector 202 compares the phase of the output signal 227 to the reference signal 201, and generates a DC error signal 203 that represents the phase difference between the two signals.
- step 1108 the charge pump 204 sources or sinks a percentage of a reference pump current 205 based the error signal 203.
- step 1110 the output current from the charge pump 204 drives the loop filter 208 to produce a tuning voltage 209.
- one or more fixed capacitors 232 are switched-in to (or switched-out of) the LC resonant circuit 228 based on the tuning voltage 209, to perform coarse frequency tuning of the selected VCO 226.
- the fixed capacitors 232 perform coarse frequency tuning by shifting the resonant frequency of the LC circuit 228, and therefore the selected VCO 226.
- the fixed capacitors 232 are switched-in to (or switched-out of) the LC circuit 228 by switching the corresponding switches 230 using the control signals 239.
- the gain compensator 800 adjusts the charge pump reference current 205 to compensate for variable VCO gain that is caused by adding or subtracting the fixed capacitors 232.
- the reference current 205 is adjusted based on the VCO control signals 239 and also the capacitor control signals 239. In embodiments, the reference current 205 is adjusted simultaneously with the switching of the fixed capacitors 232 by the capacitor control signals 239.
- the tuning voltage 209 fine tunes the frequency of the selected VCO 226 by changing voltage across the varactor 234.
- the VCO gain vs. fixed capacitance is substantially linearized by the gain compensator 800 in step 1114, thereby flattening the PLL gain and improving the PLL spectral purity.
- Flowchart 1200 further describes step 1114, where the gain compensator 800 adjusts the charge pump current to compensate for variable VCO gain.
- the order of the steps in the flowchart 1200 is not limiting as all or some of the steps can be performed simultaneously or in a different order, as will be understood by those skilled in the arts.
- the gain compensator 800 receives the VCO control signals 239 and the capacitor control signals 239.
- the VCO control signals 239 determine which VCO 226 is switched-in to the PLL 500.
- the capacitor control signals 239 determine which fixed capacitors 232 are switched-in to the LC circuit 228.
- a gain compensator cell 806 is selected to correspond to the VCO 226 that is switched-in to the PLL 500, as indicated by the VCO control signals 239. More specifically, the control signals 239 turn-on the appropriate P-FET 808 for the gain compensator cell 806 that corresponds to the selected VCO 226.
- the current scaler 804 generates a reference scale current 812 that is based on a PLL control signal 810, where the PLL control signal 810 defines certain PLL characteristics including reference frequency, loop bandwidth, and damping factor.
- step 1208 the switches 902 activate one or more groups 904 of unit current sources 906 according to the capacitor control signals 239.
- the groups 904 that are activated correspond to the capacitors 232 that are switched-in to the LC circuit 228, as indicated by the capacitor control signals 239.
- the remaining (non-selected) current sources 906 are cutoff.
- the activated groups 904 replicate (or copy) the reference scale current 812 one or more times, where the number of times that the reference scale current 812 is replicated is dependent on the capacitors 232 that are switched-in to the LC circuit 228. More specifically, the activated groups 904 replicate the reference scale current enough times to sufficiently compensate the variable VCO gain that is caused by the corresponding capacitors 232.
- step 1212 the currents from the activated current sources 906 are added together to generate the charge pump reference current 205.
- the current scaler 804 adjusts the reference scale current 812 to address changing PLL characteristics, such as reference frequency, loop bandwidth, and damping factor.
- changing PLL characteristics such as reference frequency, loop bandwidth, and damping factor.
- the gain compensation invention described herein has been discussed in reference to a tuner application. However, the gain compensation invention is not limited to tuners, and is applicable to other non-tuner applications that can benefit from flat PLL gain. Additionally, the gain compensation invention is applicable to other non-PLL circuits that can benefit from compensating for variable VCO gain. The application of the gain compensation invention to these non-PLL circuits will be understood by those skilled in the relevant arts based on the discussions given herein, and are within the scope and spirit of the present invention.
Abstract
Description
- The present invention generally relates to a gain compensator circuit, more specifically to phase lock loop gain control using scaled unit current sources, and to a method of compensating the gain of a phase lock loop.
- Radio frequency (RF) transmitters and receivers perform frequency translation by mixing an input signal with a local oscillator (LO) signal. Preferably, the LO signal should have a frequency spectrum that is as close to a pure tone as possible in order to maximize system performance during the signal mixing operation. The deviation of the LO signal from a pure tone is quantified as phase noise or phase jitter, and is generally referred to as spectral purity. In other words, a LO signal with good spectral purity has low phase noise.
- Phase-locked loops (PLLs) are often used in frequency synthesizers to generate the LO signal. A PLL frequency synthesizer produces an output signal, typically a sinewave or square wave, that is a frequency multiple of an input reference signal. The PLL output signal is also in phase synchronization with the input reference signal. PLLs are feedback loops, and therefore are susceptible to instability. Therefore, loop stability is a key performance parameter for PLLs, in addition to spectral purity of the output signal.
- A resonant-tuned voltage controlled oscillator (VCO) is typically utilized in a PLL to generate the PLL output signal. A resonant tuned VCO includes an active device and a resonant LC circuit, where the impedance of the resonant LC circuit becomes a short or an open at a resonant frequency. When the resonant circuit is connected in parallel with the active device, a positive feedback path is created in the active device at the resonant frequency of the LC circuit. The positive feedback path causes the active device to oscillate at the resonant frequency of the LC circuit.
- The resonant tuned LC circuit typically includes multiple fixed capacitors that can be switched in or out of the LC circuit, a varactor diode, and at least one inductor. The resonant frequency of the LC circuit (and therefore the oscillation frequency of the VCO) is tuned via a coarse tuning mechanism and a fine tuning mechanism. Coarse frequency tuning (or band-selection) is performed by switching one or more of the fixed capacitors in the LC circuit. Whereas, fine frequency tuning is performed by changing the voltage across the varactor diode, which produces a capacitance that varies depending on the applied tuning voltage. Both tuning mechanisms operate by changing the capacitance, and therefore the resonant frequency of the LC circuit. The varactor tuning range is slightly larger than one fixed capacitor, and therefore provides some overlap between the fixed capacitors.
- VCO gain is defined as the VCO frequency shift per unit change in the varactor tuning voltage. A problem with varactor-tuned VCOs is that the VCO gain verses fixed capacitance is variable. In other words, the VCO frequency shift verses tuning voltage is dependent on the fixed capacitance that is switched-in to the LC circuit. The variable VCO gain creates difficulties when designing a PLL because the entire PLL loop gain, bandwidth, and damping response varies with respect to the oscillator frequency. This in turn makes it difficult to optimize the output phase noise and reduces overall spectral purity. Therefore, it is desirable to compensate for the variable VCO gain, in order to maintain the overall PLL gain at a desired optimum value.
- In addition to the VCO gain, it is desirable to adjust or tune other PLL characteristics, such as loop bandwidth, reference frequency, and damping factor, without having to tune or replace PLL components.
- EP-A-0 627 820 refers to a charge pump having a reference circuitry, multiple parallel paths, a mirror circuit, a sourcing circuitry, and a sinking circuitry. The described charge pump may be incorporated into a phase locked loop circuit, where constant stability parameters are desired.
- The above and other objects are achieved by the gain compensator of
claim 1 and the method of compensating the gain of a PLL according to claim 15. - The gain compensator invention compensates for gain variation in a varactor-tuned VCO in order to maintain the overall PLL gain at a desired level over frequency. The VCO includes a LC circuit that has multiple fixed capacitors that are arranged in parallel with the varactor diode and the active portion of the VCO. The fixed capacitors are switched-in to the LC circuit by corresponding capacitor control signals. Coarse frequency tuning (also called band-select tuning) is performed by adding or subtracting one or more of the fixed capacitors to the LC circuit according to the capacitor control signal. Fine frequency tuning is performed by adjusting the tuning voltage on the varactor diode, where the VCO gain is defined as the frequency shift per unit change in varactor tuning voltage. VCO gain varies with the fixed capacitance that is switched-in to the LC circuit, and therefore changes with band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a reference charge pump current for the PLL based on information that is carried in the capacitor control signal. Therefore, the gain compensator is able to simultaneously adjust the charge pump current to maintain an overall flat PLL gain as fixed capacitors are incrementally added to (or subtracted from) the LC circuit.
- The gain compensator includes one or more cells that each correspond to a particular VCO that can be switched into the PLL at a given time. A VCO control signal selects a particular VCO for the PLL based on frequency, and also activates the appropriate cell. Each cell includes a plurality of unit current sources, where each unit current source substantially replicates (or copies) a predefined reference scale current. The unit current sources are arranged into one or more groups, where each group corresponds to a fixed capacitor in the LC circuit. Each group of unit current generates a portion of the total pump current when the corresponding capacitor is switched-in to the LC circuit. The number of unit current sources in each group is determined to compensate for the variable VCO gain that occurs when the corresponding fixed capacitor is switched-in to the LC circuit. Each group of unit current sources is activated by the same capacitor control signal that controls the corresponding fixed capacitor. Therefore, when a fixed capacitor is switched-in to the LC circuit, the corresponding group of unit current sources is simultaneously activated and switched-in to the cell to compensate for the variable VCO gain that is caused by the fixed capacitor.
- An advantage of the gain compensator invention is that the number of unit current sources that are activated for a corresponding fixed capacitor is arbitrary, but the current produced is linearly proportional to the reference scale current. In other words, there is no predefined relationship between the number of unit current sources in each group that would restrict the relative amount of current produced by each group. Therefore, the total pump current can be freely optimized to incrementally adjust for the variable VCO gain that is associated with various combinations of fixed capacitors.
- A further advantage of the gain compensator invention is that the reference scale current for the gain compensator cells is generated based on a PLL control signal. The PLL control signal specifics various PLL characteristics, such as the frequency of the reference signal, the PLL bandwidth, and the PLL damping factor, etc. Since the unit current sources are configured to replicate the reference scale current, all of the unit current sources can be simultaneously adjusted by changing the reference scale current. Therefore, the charge pump current can be efficiently adjusted to tune the mentioned characteristics of PLL for different operating conditions, without requiring the replacement of PLL components.
- Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
- The present invention is described with reference to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.
- FIG. 1A illustrates a
tuner 100 that is an example tuner environment for the present invention; - FIG. 1B illustrates dual frequency conversion that is performed by the
tuner 100; - FIG. 2 illustrates a
PLL 200 that can be used with thetuner 100; - FIG. 3 illustrates a VCO 300 that can be used with the PLL 200;
- FIG. 4 illustrates variable VCO gain;
- FIG. 5 illustrates a PLL 500 that includes a
gain compensator 502, according to embodiments of the present invention; - FIG. 6 illustrates a
ROMDAC 600 that is one embodiment of a gain compensator, according to embodiments of the present invention; - FIG. 7 illustrates a
ROMDAC 700 having an expanded look-up table 701, according to embodiments of the present invention; - FIG. 8 illustrates a
gain compensator 800 having acurrent scaler 804 that forms a current mirror configuration with one or moregain compensator cells 806, according to embodiments of the present invention; - FIG. 9 illustrates a
gain compensator cell 806 having multiple unit current sources, according to embodiments of the present invention; - FIG. 10 illustrates the
current scaler 804, according to embodiments of the present invention; - FIG. 11 illustrates a
flowchart 1100 that describes the operation of a PLL having compensation for nonlinear VCO gain, according to embodiments of the present invention; and - FIG. 12 illustrates a
flowchart 1200 that describes the operation of a gain compensator cell, according to embodiments of the present invention. - Before describing the invention in detail, it is useful to describe an example tuner application for the invention. The invention is not limited to the tuner application that is described here, and is applicable to other tuner and non-tuner applications as will be understood to those skilled in the relevant arts based on the discussions given herein.
- FIG. 1A illustrates a schematic of a
tuner assembly 100 that has an RF automatic gain control circuit (AGC) 102, and atuner 134. Thetuner assembly 100 receives anRF input signal 101 having multiple channels and down-converts a selected channel to an IF frequency, to produce an IFsignal 133. For instance, theRF input signal 101 can include multiple TV channels that typically have 6 MHZ frequency spacings and cover a range of 57-860 MHZ, and where the selected channel is down-converted to an IF frequency at 44 MHZ, 36 MHZ or some other desired IF frequency for further processing. The structure and operation of theAGC circuit 102 and thetuner 134 are described in further detail below. - The
AGC circuit 102 provides automatic gain control using avariable resistor 104 and a low noise amplifier (LNA) 106. Thevariable resistor 104 attenuates theRF input signal 101 according to acontrol signal 103. In embodiments, thecontrol signal 103 is based on the signal amplitude of the IF signal 133 so that the RF front-end gain can be adjusted to achieve a desired amplitude for theIF signal 133. TheLNA 106 provides low noise amplification and converts a single-ended input signal to adifferential RF signal 107. - The
tuner 134 has a dual conversion architecture (one up-conversion, one down-conversion) that includes aninput mixer 108 and animage reject mixer 118. Theinput mixer 108 is driven by a first phase locked loop (PLL) 110 that has coarse tuning capability from 1270-2080 MHz. The image rejectmixer 118 has twocomponent mixers second PLL 124 through a quadraturepolyphase filter 122. ThePLL 124 has a relatively fixed frequency of 1176 MHZ (for a 44 MHZ IF) and has fine frequency tuning capability. Apolyphase filter 126 is coupled to the output of the image rejectmixer 118 to combine the quadrature outputs of the mixers 120. Two separate off-chip surface acoustic wave (SAW) filters 114 and 130 are used to perform IF filtering in thetuner 134. Thefirst SAW filter 114 is connected between thefirst mixer 108 and the image rejectmixer 118. The passband of theSAW filter 114 is centered at 1220 MHZ, and is only a few channels wide (e.g. 1-3 channels wide or 18 MHZ for 6 MHZ TV channel spacings). Thesecond SAW filter 130 has a passband at 44 MHZ and is coupled to the output of thepolyphase filter 126. Additionally, various on-chip amplifiers tuner 134 to provide signal amplification, as necessary. - The operation of the
tuner 134 is described as follows and in reference to the frequency spectrum that is illustrated in FIG.1B. Thefirst mixer 108 mixes the RF signal 107 with aLO signal 109 that is generated by thePLL 110. Since thePLL 110 is tunable from 1270-2080 MHZ, theRF signal 107 is up-converted to a first IF 111 having a frequency that is above the 57-860 MHZ input frequency band. The first IF 111 is sent off-chip to theSAW filter 114, which has a narrow passband window centered at 1220 MHz. Thefirst SAW filter 114 selects a desiredchannel 115 that is within its narrow passband window, and substantially rejects all of the remaining channels. Therefore, a particular channel is selected by varying the frequency of the LO signal 109 so that the desired channel is up-converted into the narrow passband of theIF filter 114. The desired channel 115 (at 1220 MHZ) is sent back on-chip to the image rejectmixer 118 that is driven by a quadrature LO signal 119 from thepolyphase filter 122. The image rejectmixer 118 down-converts the desiredchannel 115 to a 44 MHZ IFsignal 127 that appears at the output of thepolyphase filter 126, where I and Q components of the IF signal 127 are combined in thepolyphase filter 126. Finally, theIF signal 127 is filtered a second time by thebandpass SAW filter 130 to reject any unwanted frequency harmonics, producing the output IFsignal 133 at 44 MHZ and carrying the information in the desired channel. - The specific frequencies mentioned in the description of the
tuner assembly 100, and throughout this application, are given for example purposes only and are not meant to be limiting. Those skilled in the arts will recognize other frequency applications for thetuner assembly 100 based on the discussion given herein. These other frequency applications are within the scope and spirit of the present invention. - The
first PLL 110 and thesecond PLL 124 are represented by thePLL 200 that is illustrated in FIG. 2. ThePLL 200 generates aPLL output signal 227 that is a frequency multiple of areference signal 201, and where theoutput signal 227 is phase-locked to thereference signal 201. ThePLL 200 self-corrects for any phase (and therefore frequency) variations between thereference signal 201 and theoutput signal 227 via a feedback mechanism that is described as follows. The structure and operation of thePLL 200 are described as follows. - The
PLL 200 structure includes: aphase detector 202, acharge pump 204, afrequency divider 206, aloop filter 208, acoarse tuning circuit 214, aVCO assembly 222, and a LCresonant circuit 228. Theloop filter 208 includes avariable resistor 210 and avariable capacitor 212 that are controlled by an I2C signal 207. Thecoarse tuning circuit 214 includes acomparator 216 and ashift register 218. TheVCO assembly 222 includesmultiple component VCOs 226a-c, where eachVCO 226 preferably covers a particular frequency band. AVCO 226 is switched-in to thePLL 200 by closing a corresponding switch 224. The switches 224a-c are controlled by corresponding control signals 223a-c that make-up aVCO control bus 220. The LCresonant circuit 228 is connected in parallel with theVCO assembly 222 and includes: multiple fixed capacitors 232an having correspondingswitches 230a-n, avaractor 234, and aninductor 236. One or more of the fixed capacitors 232 are switched in-parallel with the selectedVCO 226 by closing the corresponding switch(s) 230. The switches 230 are controlled by correspondingcontrol signals 239a-n that make-up acapacitor control bus 238. -
- As discussed further below, coarse frequency tuning (e.g. band-selection) of the selected
VCO 226 is performed by switching in one or more of the fixed capacitors 232 into theLC circuit 228. This changes the resonant frequency of theLC circuit 228, and therefore the oscillation frequency of the selectedVCO 226. Fine frequency tuning is performed by changing the control voltage on thevaractor 234, which has a variable capacitance that changes with applied voltage. The VCO gain is defined as the change in the VCO output frequency per unit change in the voltage across thevaractor 234. - The
PLL 200 operates based on known PLL feedback principles. AVCO 226 is selected based on the desired frequency of operation for thePLL 200, and is switched-in to thePLL 200 by closing the appropriate switch 224 using the appropriate control signal 223. The PLL output signal 227 from the selectedVCO 226 is fed back to aphase detector 202 through thefrequency divider 206. Thefrequency divider 206 normalizes the frequency of theoutput signal 227 to that of thereference signal 201 for comparison in thephase detector 202. Thephase detector 202 compares the phase of theoutput signal 227 to thereference signal 201, and generates aDC error signal 203 that represents the phase difference between the two signals. Thecharge pump 204 receives theerror signal 203 and a reference pump current 205. Thecharge pump 204 sources (or sinks) a percentage of the pump current 205 based on theerror signal 203, as will be understood by those skilled in the arts. The output current of thecharge pump 204 drives theloop filter 208 to produce atuning voltage 209. Part of thetuning voltage 209 is dropped across thevariable capacitor 212 to generate atuning voltage 211. As discussed further below, the tuningvoltages VCO 226. - The tuning
voltages coarse tuning circuit 214 adds (or subtracts) one or more of the fixedcapacitors 232a-n to theLC circuit 228 based on thetuning voltage 211. Similarly, thetuning voltage 209 directly adjusts the voltage (and therefore the capacitance) of thevaractor 234 to implement fine frequency tuning. Both tuning mechanisms adjust the oscillation frequency of theVCO 226 by changing the capacitance of theLC circuit 228, which shifts the resonant frequency of theLC circuit 228. The tuning range of thevaractor 234 is slightly larger than one fixed capacitor 232, and therefore provides some tuning overlap between the fixed capacitors 232. Thecoarse tuning circuit 214 is described further below. - The
coarse tuning circuit 214 includes awindow comparator 216 and abi-directional shift register 218. Thewindow comparator 216 receives thetuning voltage 211 and also receives input reference voltages v1 and v2. Thewindow comparator 216 determines if thevoltage 211 is within a voltage "window" that is defined between the input references voltages v1 and v2, and generates acontrol signal 217 that controls thebi-directional shift register 218 based on this determination. Theshift register 218 stores a series of bits that control the capacitor switches 230 via thecontrol bus 238 to add (or subtract) the corresponding capacitors 232 to (or from) theLC circuit 228. A "1" bit on the control line 239 causes the corresponding switch 230 to close and thereby adds the corresponding capacitor 232 to theLC circuit 228. A "0" bit on the control line 239 causes the switch 230 to open and thereby subtracts the corresponding capacitor 232 from theLC circuit 228. - The
coarse tuning circuit 214 operates to self-correct coarse variations in the oscillation frequency of the selectedVCO 226 by adding or subtracting capacitors 232, based on thetuning voltage 211. If thecomparator 216 determines that thevoltage 211 is below v1, then thecomparator 216 causes a series of "1"s to be shifted through theshift register 218, which incrementally adds capacitors 232 to theLC circuit 228 until thetuning voltage 211 is within the v1-to-v2 voltage window. If thecomparator 216 determines that thevoltage 211 is above the voltage v2, then thecomparator 216 causes a series of "0"s to be shifted through theshift register 218, which incrementally subtracts capacitors 232 from theLC circuit 228 until thetuning voltage 211 is within the v1-to-v2 voltage window. As described above, the frequency of the selectedoscillator 226 changes whenever capacitance is added to, or subtracted from, theLC circuit 228. If thecomparator 216 determines that thevoltage 211 is within the voltage window defined by v1 and v2, then no action is taken and the fixed capacitance in theLC circuit 228 remains unchanged. In other words, thetuning voltage 211 is within an acceptable voltage range (or "window"), and correspondingly, the frequency of theoutput signal 227 is within an acceptable frequency range. Therefore the number of the fixed capacitors 232 that are switched-in to theLC circuit 228 is not changed. - FIG. 3 illustrates a
differential VCO 300 as one embodiment ofVCO 226 and the LCresonant circuit 228. TheVCO 300 is meant for example purposes only and is not meant to limit the invention in any way. Other oscillator configurations could be utilized to practice the invention, as will be understood by those skilled in the relevant arts based on the discussions given herein. - The
VCO 300 includes theactive VCO portion 226 and theresonant LC circuit 228. The active portion includes a pair of cross coupledtransistors LC circuit 228. In this cross-coupled configuration, the drain oftransistor 302a is connected to the gate oftransistor 302b. Likewise, the drain oftransistor 302b is connected to the gate of thetransistor 302a. TheLC circuit 228 is also coupled to the drains of the transistors 302. At resonance, theLC circuit 228 causes a positive feedback path between the cross-coupled transistors 302, which causes the transistors to oscillate at the resonant frequency of theLC circuit 228, producing thedifferential output signal 227. - The oscillation frequency of the
VCO 300 can be tuned by two mechanisms. Coarse frequency tuning (or band selection) is performed by adding or subtracting the fixed capacitors 232 using the corresponding switches 230. Fine frequency tuning is performed by thetuning voltage 209, which varies the capacitance produced by the series-connectedvaractor diodes VCO 300 per unit change invaractor 234 voltage is defined as the VCO gain. As stated above, the tuning range of thevaractor 234 is slightly larger than the capacitance of one fixed capacitor 232, and therefore provides some tuning overlap between the fixed capacitors 232. - In one embodiment, the
varactors 234 are PN junction varactors, and in an alternate embodiment thesevaractors 234 are MOSFET varactors, depending on the designer's preference. -
- KPHl = Phase detector gain (mA/radian)
- RLF = Loop filter resistance
- CLF = Loop filter capacitance
- KVCO = VCO gain (MHZ/volt)
- s represents frequency
- The feedback PLL gain H(s) = 1/N, where N is the feedback frequency division ratio. The overall open loop gain is G(s)H(s), and the overall closed-loop gain is G(s)/[1+G(s)H(s)].
- As described above, the
PLL 200 performs coarse frequency tuning by incrementally adding (or subtracting) one or more of the fixed capacitors 232 that are in-parallel with the selectedVCO 226. Fine frequency tuning is performed by adjusting the voltage on thevaractor 234, where the VCO gain is defined as the frequency shift per unit change in thetuning voltage 209. A problem with varactor-tuned VCOs is that the VCO gain verses the fixed capacitance 232 is variable. FIG.4 illustrates this characteristic with a graph of VCO gain 402 verses fixed capacitance. As shown, theVCO gain curve 402 is reduced for a large fixed capacitance and is increased for a small fixed capacitance. Variable VCO gain is undesirable because it causes the PLL forward gain to change according to Eq. 2. In VCO applications with a large minimum-to-maximum capacitance tuning range, this VCO gain variability can cause loop instability, and reduced spectral purity in the PLL output signal. In a preferred embodiment, the VCO gain variability is compensated for by acompensator gain 404 so that the overall PLL gain 406 remains relatively flat for variations in fixed capacitance (and therefore VCO frequency). More specifically, the charge pump current 205 is compensated to counter the variable VCO gain so that the overall PLL gain is flat. - FIG. 5 illustrates a
PLL 500 that has again compensator 502 to adjust the charge pump current 205 in order to linearize (and flatten) the overall PLL gain of thePLL 500. Thegain compensator 502 generates the pump current 205 based on the control information carried by theVCO control bus 220 and thecapacitor control bus 238. As discussed above, theVCO control bus 220 selects theappropriate VCO 226 based on the desired frequency range for thePLL output signal 227. Thecapacitor control bus 238 selects the fixed capacitors 232 that are switched-in parallel with the selectedVCO 226 for coarse frequency tuning of theVCO 226. Therefore, thegain compensator 502 can tailor the reference pump current 205 for a specifiedVCO 226 at a specified fixed capacitance 232 value, and thereby compensate for the variable VCO gain vs. fixed capacitance. - FIG 6 illustrates a read only memory digital-to-analog converter (ROMDAC) 600 that is one example embodiment of the
gain compensator 502, according to embodiments of the invention. Referring to FIG.6, theROMDAC 600 includes a look-up table 602 and a current digital-to-analog converter 610. The lookup table 602 stores pump current values 604a-n that are indexed by the selectedVCO 226 and a fixed capacitance total 606, where the fixed capacitance total 606 is the parallel sum of the capacitors 232 that are switched-in to theLC circuit 228. The pump current values 604 are selected to compensate for the variable VCO gain vs. capacitance, given an identifiedVCO 226 and the fixed capacitance total 606. Preferably, thePLL 200 is characterized beforehand for eachVCO 226 to determine the pump current values 604 that produces a flat overall PLL gain for various capacitance totals 606. The look-up table 602 outputs a pumpcurrent value 608 that corresponds to identifiedVCO 226 and the fixed capacitance total 606. TheDAC 610 converts the pumpcurrent value 608 to the actual analog pump current 205 that drives thecharge pump 204. As capacitors 232 are added to or subtracted from theLC circuit 228, the lookup table 602 selects the appropriate pump current value 604 so as to maintain a flat overall PLL gain. Therefore, the pump current 205 is adjusted for various total capacitance 606 to counteract the variable gain of the selectedVCO 226, and thereby flatten the overall gain of thePLL 500. - An advantage of the
ROMDAC 600 is that the pump current values 604 can be totally arbitrary and mathematically unrelated to each other. In other words, the pump currents 604 can be individually selected to produce an optimum overall PLL gain for a givenVCO 226 and capacitance total 606, without being restricted by any mathematical relationship. In an alternate embodiment, the various pump currents 604 are mathematically related to each other, or to theVCO control signal 220 or thecapacitor control signal 238. - In addition to PLL gain, it is desirable to tune various other PLL characteristics, such input reference frequency, loop bandwidth, damping factor, etc. This allows the same PLL to be used in different operating environments. For instance, it is often desirable to have a PLL configuration that is operable with a number of different reference frequencies. If the frequency of the
reference signal 201 increases by factor of two, the PLL loop gain should preferably be adjusted to compensate for this increase so that the PLL loop remains stable and accurate. The PLL loop gain can be appropriately adjusted by reducing the frequency division of thefrequency divider 206 by a factor of two. However, this would require replacement of thefrequency divider 206 for each possible reference frequency, or the use of a programable frequency divider. Alternatively, the charge pump current could be reduced by a factor of two to get the same effect. - FIG. 7 illustrates a
ROMDAC 700 as another embodiment of thegain compensator 502, according to embodiments of the present invention. TheROMDAC 700 has an expanded lookup table 701 that hasmultiple sets 710a-d of pump current values, where the sets 710 tune various PLL characteristics in addition to compensating for variable VCO gain. Some PLL characteristics include, but are not limited to, PLL reference signal frequency, loop bandwidth, loop damping, etc. For example, sets 710a and 710b have pump current values 702a-n and 704a-n, respectively, which are customized for different reference frequencies. The pump current values 702a-n can correspond to afirst reference signal 201 frequency, and the pump current values 704a-n can correspond to asecond reference signal 201 frequency. Therefore, if the frequency of thereference signal 201 changes, then the pumpcurrent value 608 can be selected from the appropriate pump current set 710. In another example, the pumpcurrent sets variable resistor 210 in theloop filter 208, which also determines the loop bandwidth. If the damping factor is changed, then the loop bandwidth can be held constant by selecting theappropriate set - To summarize, by storing multiple sets 710 of charge pump values in the lookup table 701, multiple PLL characteristics can be adjusted or tuned in addition to PLL gain. This allows the
same PLL 500 to be used under different PLL operating conditions, without replacing PLL components. The number of pump current sets 710 can be expanded to adjust any number of PLL characteristics, assuming there is sufficient memory space in the look-up table 701. - FIG. 8 illustrates a
gain compensator 800 that is another embodiment of thegain compensator 502 in FIG. 5. Thegain compensator 800 includes: avoltage generator 801, gaincompensator cells 806a-c that correspond toVCOs 226a-c, andPFETs 808a-c that correspond to thegain compensator cells 806a-c. Each gaincompensator cell 806 generates a prospective pump current 807 that compensates for the variable VCO gain of itscorresponding VCO 226 caused by the fixed capacitors 232. Since only oneVCO 226 is operational at a given time, only one prospective pump current 807 becomes the actual pump current 205 that feeds thecharge pump 204. The PFETs 808 operate as switches that are controlled by the VCO control signals 239 and select the appropriate prospective pump current 807 to correspond with the selectedVCO 226. For example, if theVCO 226a is the selectedVCO 226, then thecontrol signal 239a causes thePFET 808a to conduct so that the current 807a becomes the feed for the pump current 205. Accordingly, control signals 239b and 239c cutoff theirrespective PFETs - The structure of the
gain compensator cell 806 is shown in FIG 9 and includes: switches 902a-d that are controlled by the respectivecapacitor control signals 239a-d, and unitcurrent sources 906a-j that are arranged in groups 904a-d. Preferably, each unit current source 906 generates substantially the same amount of unit current (within transistor tolerances), where the amount of unit current is based on agate voltage 805 that is generated by the voltage generate 801. Each group 904 corresponds to a capacitor 232, and generates a portion of the total pump current 205 when the respective capacitor 232 is switched-in to theLC circuit 228. The number of unit current sources 906 in each group 904 is selected to compensate for the variable VCO gain that occurs when the corresponding capacitor 232 is switched-in to theLC circuit 228. For example, group 904a corresponds tocapacitor 232a, and has 4 unit current sources 906 to compensate for variable VCO gain that is caused by thecapacitor 232a. Whereas,group 904b only has 2 unit current sources 906 to address the variable VCO gain caused by thecapacitor 232b, and so on. Note that the number ofcurrent sources - A group 904 is switched into the
gain compensator cell 806 when the corresponding switch 902 connectsVg 805 to the unit current sources 906 in the group 904. Once connected to a group 904, theVg 805 activates the current sources 906 and determines the current produced by each current source 906. The switches 902 are controlled by the same capacitor control signals 239 that switches-in the respective capacitors 232 into theLC circuit 228. Therefore, when a capacitor 232 is switched-in to theLC circuit 228, the corresponding group 904 will be switched-in to thegain compensator cell 806, and therefore contribute to the prospective pump current 807. For instance, if thecapacitor 232a is switched-in to theLC circuit 228 by thecapacitor control signal 239a, then the group 904a of unit current sources 906 will be switched-in to thegain compensator cell 806 by thesame control signal 239a. Therefore, the current from the group 904a will contribute to the prospective pump current 807, and thereby compensate for the variable VCO gain that is caused by thecapacitor 232a. If thecapacitor 232b is then switched-in to theLC circuit 228, then thegroup 904b is switched-in to thegain compensator cell 806 to compensate for the variable VCO gain that is caused by thecapacitor 232b. As such, the charge pump current 205 is simultaneously adjusted to maintain a flat overall PLL as the capacitors 232 are incrementally added to (or subtracted from) theLC circuit 228. - Each unit current source 906 is preferably a PFET transistor, as shown. However, other transistor devices and configurations could be used for the unit current sources 906, including N-FET transistors, as will be understood by those skilled in the relevant arts based on the discussions given herein. These other transistor devices and configurations are within the scope and spirit of the present invention. For example, simultaneous use of NFET and PFET current sources would permit the gain compensator to compensate for a non-monotonic VCO gain verses fixed capacitance characteristic.
- The
voltage generator 801 and the current sources 906 operate as a "current mirror", where the drain currents of the selected unit current sources 906 copy or "mirror" a reference scale current 812. More specifically, thecurrent scaler 804 sets the reference scale current 812, which operates as a current sink for thePFET 802. ThePFET 802 operates as a diode because the gate and drain of thePFET 802 are shorted together by aconductor 813. The drain current 814 of thePFET 802 is substantially the same as the reference scale current 812 because there is substantially zero current on theconductor 813. The diode-connectedPFET 802 generates thegate voltage 805 at its gate terminal to correspond with the drain current 814, and therefore to the reference scale current 812. If the drain current 814 deviates from the reference scale current 812 for some reason, then charge flows to/from the gate of thePFET 802 to bring the current 814 and the scale current 812 back in-line with each other. Thegate voltage 805 is applied to the gate of the current sources 906 when their respective group 904 is selected by the capacitor control signals 239. The current sources 906 will reproduce (or "mirror") the drain current 814 due to thecommon gate voltage 805, if the device characteristics of the current sources 906 are sufficiently similar to those of thePFET 802. This current mirror effect occurs because two or more FETs that have a common gate-to-source voltage and similar device characteristics will generate substantially the same drain current. If a group 904 is not switched-in by the corresponding capacitor control signal 239 (because the corresponding capacitor 232 is not switched in the LC circuit 228), then the gates of the corresponding current sources 906 are connected to Vcc by the corresponding switch 902. When connected to Vcc, these non-selected current sources 906 are cutoff and do not generate a unit current. - Preferably, the
PFET 802 and the current sources 906 are fabricated on the same semiconductor wafer using the same process, which improves the commonality of device characteristics. However, if the size of the unit current sources 906 is scaled relative to the size of thePFET 802, then the unit current sources 906 will generate a current that is proportional to the scale factor, as will be understood by those skilled in the relevant arts. This increases the flexibility of thegain compensator cell 806, as the current sources 906 can be scaled relative to thePFET 802 as well as relative to each other. - The
current scaler 804 sets the reference scale current 812 based on aPLL control signal 810, where thePLL control signal 810 dictates various PLL characteristics such as the frequency of thereference signal 201, the PLL loop bandwidth, and PLL loop damping, etc. FIG. 10 illustrates one embodiment of thecurrent scaler 804 and includes weightedcurrent sources 1002a-n. The weightedcurrent sources 1002a-n sink currents 1004a-n based the PLL variables in thePLL control signal 810. For example, thecurrent source 1002a can be adapted to generate a current 1004a that is proportional to the frequency of thereference signal 201, and thecurrent source 1002b can be adapted to generate a current 1004b that is proportional to the desired loop bandwidth, etc. Thecurrents 1004a-n are summed together to form the reference scale current 812 that feeds the diode-connectedPFET 802. Therefore, changes in the PLL variables are reflected in the reference scale current 812, and ultimately in the drain currents of the unit current sources 906 because of the current mirror effect described herein. More specifically, the PFET drain current 814 is substantially the same as the reference scale current 812, and gets copied to the drain currents of the unit current sources 906. - An advantage of using the
current scaler 800 is that all of the current sources 906 (that are in a selected group 904) are simultaneously adjusted for changing PLL characteristics, in addition to compensating for variable VCO gain. Therefore, the prospective pump current 807 (and ultimately the final pump current 205) can be efficiently tuned to compensate for changing PLL characteristics. This allows the same PLL to be utilized under different operating conditions. Furthermore, thecurrent scaler 804 reduces the size of the overall gain compensator because multiple sets of current sources 906 are not needed to address changing PLL characteristics. In contrast, theROMDAC 700 requires multiple sets 710 of current values to address changing PLL characteristics, which increases the size of theROMDAC 700. - The following examples illustrate the flexibility of the
PLL 500 when using thecurrent scaler 804 to adjust for changing PLL characteristics (besides VCO gain). In a first example, the frequency of thereference signal 201 increases by a factor of two, but thefrequency divider 206 ratio is to remain constant. The same thefrequency divider 206 can be used in thePLL 500 if the charge pump current 205 is reduced by approximately a factor of two. This is accomplished by reducing the reference scale current 812 that is generated by thecurrent scaler 804, causing a corresponding reduction in thegate voltage 805. Through the current mirror effect, the current produced by the selected current sources 906 will be proportionally reduced by a factor of two. Therefore, the prospective current 807 (and the pump 205) will also be reduced by a factor of two as desired, and thesame PLL 500 can be reused for the new reference frequency. - In a second example, the PLL damping factor ζ is to be increased, but the PLL bandwidth is to be held constant. The PLL damping factor ζ is increased by increasing the resistance of the
variable resistor 210 in theloop filter 208. However, this also changes the loop bandwidth as will be understood by those skilled in the arts. To compensate, thecurrent scaler 804 adjusts the reference scale current 812, and therefore the unit current sources 906 to produce a reference pump current 205 that compensates for the loop bandwidth. - In summary, and based on the examples herein, the
gain compensator 800 is able to compensate for variable VCO gain and simultaneously tune other PLL characteristics by using the current mirror configuration described herein. These other PLL characteristics include but are not limited to changes in reference frequency, damping factor, and bandwidth. - The
flowchart 1100 further describes the operation of thegain compensator 800 and VCO gain compensation according to embodiments of the present invention. The order of the steps in theflowchart 1100 is not limiting as all or some of the steps can be performed simultaneously or in a different order, as will be understood by those skilled in the arts. - In
step 1102, aVCO 226 is selected from theVCO 226a-c based on the desired frequency of theoutput signal 227. The selection is made by closing the appropriate switch 230 using the control signals 239 to switch-in the desiredVCO 226. - In
step 1104, theVCO output signal 227 is fed back to thephase detector 202 through afrequency divider 206. Thefrequency divider 206 normalizes the frequency of theoutput signal 227 to that of thereference signal 201 for comparison in thephase detector 202. - In
step 1106, thephase detector 202 compares the phase of theoutput signal 227 to thereference signal 201, and generates aDC error signal 203 that represents the phase difference between the two signals. - In
step 1108, thecharge pump 204 sources or sinks a percentage of a reference pump current 205 based theerror signal 203. - In
step 1110, the output current from thecharge pump 204 drives theloop filter 208 to produce atuning voltage 209. - In
step 1112, one or more fixed capacitors 232 are switched-in to (or switched-out of) the LCresonant circuit 228 based on thetuning voltage 209, to perform coarse frequency tuning of the selectedVCO 226. The fixed capacitors 232 perform coarse frequency tuning by shifting the resonant frequency of theLC circuit 228, and therefore the selectedVCO 226. The fixed capacitors 232 are switched-in to (or switched-out of) theLC circuit 228 by switching the corresponding switches 230 using the control signals 239. - In
step 1114, thegain compensator 800 adjusts the charge pump reference current 205 to compensate for variable VCO gain that is caused by adding or subtracting the fixed capacitors 232. The reference current 205 is adjusted based on the VCO control signals 239 and also the capacitor control signals 239. In embodiments, the reference current 205 is adjusted simultaneously with the switching of the fixed capacitors 232 by the capacitor control signals 239. - In
step 1116, thetuning voltage 209 fine tunes the frequency of the selectedVCO 226 by changing voltage across thevaractor 234. The VCO gain vs. fixed capacitance is substantially linearized by thegain compensator 800 instep 1114, thereby flattening the PLL gain and improving the PLL spectral purity. -
Flowchart 1200 further describesstep 1114, where thegain compensator 800 adjusts the charge pump current to compensate for variable VCO gain. The order of the steps in theflowchart 1200 is not limiting as all or some of the steps can be performed simultaneously or in a different order, as will be understood by those skilled in the arts. - In
step 1202, thegain compensator 800 receives the VCO control signals 239 and the capacitor control signals 239. The VCO control signals 239 determine whichVCO 226 is switched-in to thePLL 500. The capacitor control signals 239 determine which fixed capacitors 232 are switched-in to theLC circuit 228. - In
step 1204, again compensator cell 806 is selected to correspond to theVCO 226 that is switched-in to thePLL 500, as indicated by the VCO control signals 239. More specifically, the control signals 239 turn-on the appropriate P-FET 808 for thegain compensator cell 806 that corresponds to the selectedVCO 226. - In
step 1206, thecurrent scaler 804 generates a reference scale current 812 that is based on aPLL control signal 810, where thePLL control signal 810 defines certain PLL characteristics including reference frequency, loop bandwidth, and damping factor. - In
step 1208, the switches 902 activate one or more groups 904 of unit current sources 906 according to the capacitor control signals 239. The groups 904 that are activated correspond to the capacitors 232 that are switched-in to theLC circuit 228, as indicated by the capacitor control signals 239. The remaining (non-selected) current sources 906 are cutoff. - In
step 1210, the activated groups 904 replicate (or copy) the reference scale current 812 one or more times, where the number of times that the reference scale current 812 is replicated is dependent on the capacitors 232 that are switched-in to theLC circuit 228. More specifically, the activated groups 904 replicate the reference scale current enough times to sufficiently compensate the variable VCO gain that is caused by the corresponding capacitors 232. - In
step 1212, the currents from the activated current sources 906 are added together to generate the charge pump reference current 205. - In
step 1214, thecurrent scaler 804 adjusts the reference scale current 812 to address changing PLL characteristics, such as reference frequency, loop bandwidth, and damping factor. By adjusting the reference scale current 812, all of the replicated currents instep 1210 are simultaneously adjusted to address the changing PLL characteristics. - The gain compensation invention described herein has been discussed in reference to a tuner application. However, the gain compensation invention is not limited to tuners, and is applicable to other non-tuner applications that can benefit from flat PLL gain. Additionally, the gain compensation invention is applicable to other non-PLL circuits that can benefit from compensating for variable VCO gain. The application of the gain compensation invention to these non-PLL circuits will be understood by those skilled in the relevant arts based on the discussions given herein, and are within the scope and spirit of the present invention.
Claims (17)
- A gain compensator circuit (502) that determines a reference pump current (205) for a charge pump (204) in a phase lock loop (PLL) (500), comprising:a plurality of unit current sources (906 a-j) that are arranged into at least one group (904 a-d), said group (904 a-d) responsive to a capacitor control signal (239 a-d) and generating a portion of the reference pump current (205) when said group (904 a-d) is activated, wherein said capacitor control signal (239 a-d) also controls a corresponding fixed capacitor (232 a-n) comprised in a VCO tuning circuit for tuning a frequency of a VCO; andmeans for scaling(804) said unit current sources (906 a-j) responsive to a phase lock loop control signal (810).
- The gain compensator circuit (502) of claim 1, wherein a number of said unit current sources (906 a-j) in said group (904 a-d) corresponds to a capacitance of said corresponding fixed capacitor (232 a-n).
- The gain compensator circuit (502) of claim 1, wherein a number of said unit current sources (906 a-j) in said group (904 a-d) is determined so as to compensate for variable VCO gain that is caused by said fixed capacitor (232 a-n).
- The gain compensator circuit (502) of any of claims 1 to 3, wherein said fixed capacitor (232 a-n) determines a resonant frequency of a resonant circuit.
- The gain compensator circuit (502) of claim 4, wherein said resonant frequency determines an oscillation frequency of a VCO.
- The gain compensator circuit (502) of any of claims 1 to 5, wherein said capacitor control signal (239 a-d) switches-in said fixed capacitor (232 a-n) and activates said group (904 a-d) of said unit current sources (906 a-j).
- The gain compensator circuit (502) of any of claims 1 to 6, wherein said unit current sources (906 a-j) replicate a reference scale current (812), wherein the number of times said reference scale current (812) is replicated is based on a total fixed capacitance that is switched-in to a resonant circuit.
- The gain compensator circuit (502) of claim 7, wherein said means for scaling (804) adjusts said reference scale current (812) based on said PLL control signal (810).
- The gain compensator circuit (502) of claim 8, wherein said means for scaling comprises one or more weighted current sources that are responsive to said PLL control signal (810).
- The gain compensator circuit (502) of claim 9, wherein said PLL control signal (810) indicates at least one of reference frequency, bandwidth, and damping factor of said PLL (500).
- The gain compensator circuit (502) of any of claims 1 to 10, wherein said means for scaling (804) and said unit current sources (906 a-j) form a current mirror.
- The gain compensator circuit (502) of any of claims 1 to 11, wherein each unit current source (906 a-j) is a field effect transistor (FET) that is controlled by said means for scaling (804) when said unit current sources (906 a-j) are activated.
- The gain compensator circuit (502) of claim 12, wherein said means for scaling (804) comprises a means for generating a gate voltage that is applied to a gate of said FETs when said group (904 a-d) is activated.
- The gain compensator circuit (502) of claim 12, wherein said means for scaling (804) comprises a means for generating a gate voltage based on said PLL control signal (810), and wherein said gain compensator circuit (502) further comprises:a switch that is connected to said group (904 a-d) of unit current sources (906 a-j), wherein said switch applies said gate voltage to said group (904 a-d) of unit current sources (906 a-j) when said corresponding fixed capacitor (232 a-n) is switched-in to a resonant circuit.
- A method of compensating the gain of a phase lock loop (PLL) (500), comprising the steps of:(1) generating a reference scale current (812);(2) switching a fixed capacitor (232 a-n) into a VCO tuning circuit that is part of a VCO to tune a frequency of said VCO;(3) replicating said reference scale current (812) a number of times when said fixed capacitor (232 a-n) is switched-in to said VCO tuning circuit, wherein the number of times said reference scale current (812) is replicated is based on said fixed capacitor (232 a-n);(4) contributing said replicated currents to a reference charge pump current (205) for said PLL (500); and(5) adjusting said reference scale current (812) based on a PLL control signal (810) that indicates characteristics of said PLL (500).
- The method of claim 15, wherein step (5) comprises the step of adjusting one or more weighted current sources that generate said reference scale current (812) based on said PLL control signal (810).
- The method of claim 15 or claim 16, wherein said PLL characteristics include at least one of reference frequency, PLL bandwidth, and PLL damping factor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05013611A EP1592135A1 (en) | 2001-03-20 | 2002-03-20 | Phase lock loop gain control using unit current sources |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/811,611 US6583675B2 (en) | 2001-03-20 | 2001-03-20 | Apparatus and method for phase lock loop gain control using unit current sources |
US811611 | 2001-03-20 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05013611A Division EP1592135A1 (en) | 2001-03-20 | 2002-03-20 | Phase lock loop gain control using unit current sources |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1244215A1 EP1244215A1 (en) | 2002-09-25 |
EP1244215B1 true EP1244215B1 (en) | 2007-05-23 |
Family
ID=25207041
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05013611A Withdrawn EP1592135A1 (en) | 2001-03-20 | 2002-03-20 | Phase lock loop gain control using unit current sources |
EP02252014A Expired - Lifetime EP1244215B1 (en) | 2001-03-20 | 2002-03-20 | Phase lock loop gain control using unit current sources |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP05013611A Withdrawn EP1592135A1 (en) | 2001-03-20 | 2002-03-20 | Phase lock loop gain control using unit current sources |
Country Status (4)
Country | Link |
---|---|
US (13) | US6583675B2 (en) |
EP (2) | EP1592135A1 (en) |
AT (1) | ATE363155T1 (en) |
DE (1) | DE60220209T2 (en) |
Families Citing this family (166)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6374311B1 (en) * | 1991-10-01 | 2002-04-16 | Intermec Ip Corp. | Communication network having a plurality of bridging nodes which transmit a beacon to terminal nodes in power saving state that it has messages awaiting delivery |
US7415548B2 (en) | 1991-05-13 | 2008-08-19 | Broadcom Corporation | Communication network having a plurality of bridging nodes which transmits a polling message with backward learning technique to determine communication pathway |
US7558557B1 (en) * | 1991-11-12 | 2009-07-07 | Broadcom Corporation | Low-power messaging in a network supporting roaming terminals |
DE69232639T2 (en) * | 1991-10-01 | 2003-02-20 | Norand Corp | LOCAL RADIO FREQUENCY NETWORK |
US7917145B2 (en) * | 1992-11-02 | 2011-03-29 | Broadcom Corporation | Radio frequency local area network |
US8509260B2 (en) | 1993-08-31 | 2013-08-13 | Broadcom Corporation | Modular, portable data processing terminal for use in a communication network |
US7217615B1 (en) * | 2000-08-31 | 2007-05-15 | Micron Technology, Inc. | Capacitor fabrication methods including forming a conductive layer |
US20030232613A1 (en) * | 2001-01-12 | 2003-12-18 | Kerth Donald A. | Quadrature signal generation in radio-frequency apparatus and associated methods |
US20020127992A1 (en) * | 2001-03-08 | 2002-09-12 | Fransis Bert L. | Wideband local oscillator architecture |
US20020127985A1 (en) * | 2001-03-08 | 2002-09-12 | Fransis Bert L. | Wideband local oscillator architecture |
US6583675B2 (en) * | 2001-03-20 | 2003-06-24 | Broadcom Corporation | Apparatus and method for phase lock loop gain control using unit current sources |
KR20030019565A (en) * | 2001-05-11 | 2003-03-06 | 코닌클리즈케 필립스 일렉트로닉스 엔.브이. | Integrated tuner circuit |
US7133485B1 (en) | 2001-06-25 | 2006-11-07 | Silicon Laboratories Inc. | Feedback system incorporating slow digital switching for glitch-free state changes |
US6753738B1 (en) * | 2001-06-25 | 2004-06-22 | Silicon Laboratories, Inc. | Impedance tuning circuit |
DE10134640B4 (en) * | 2001-07-17 | 2005-07-14 | Texas Instruments Deutschland Gmbh | PLL circuit and method for automatically setting its output frequency |
US7171170B2 (en) | 2001-07-23 | 2007-01-30 | Sequoia Communications | Envelope limiting for polar modulators |
US6920316B2 (en) * | 2001-09-04 | 2005-07-19 | Freescale Semiconductor, Inc. | High performance integrated circuit regulator with substrate transient suppression |
JP2003087116A (en) * | 2001-09-14 | 2003-03-20 | Nec Saitama Ltd | Pll synthesizer |
JP2003110357A (en) * | 2001-09-28 | 2003-04-11 | Toshiba Corp | Oscillator circuit, and semiconductor device having the same oscillator circuit |
US6985703B2 (en) | 2001-10-04 | 2006-01-10 | Sequoia Corporation | Direct synthesis transmitter |
US7333791B2 (en) * | 2001-12-11 | 2008-02-19 | Microtune (Texas), L.P. | Use of an image reject mixer in a forward data channel tuner |
JP3832643B2 (en) * | 2002-01-10 | 2006-10-11 | シャープ株式会社 | High frequency receiver |
US6836192B1 (en) * | 2002-01-16 | 2004-12-28 | Microtune (San Diego), Inc. | Methods and apparatuses for tuning voltage controlled oscillators |
GB2384927A (en) * | 2002-02-05 | 2003-08-06 | Zarlink Semiconductor Ltd | Voltage controlled oscillators |
US6825785B1 (en) * | 2002-02-28 | 2004-11-30 | Silicon Laboratories, Inc. | Digital expander apparatus and method for generating multiple analog control signals particularly useful for controlling a sub-varactor array of a voltage controlled oscillator |
US6856205B1 (en) * | 2002-04-17 | 2005-02-15 | Sequoia Communications | VCO with automatic calibration |
US7489916B1 (en) | 2002-06-04 | 2009-02-10 | Sequoia Communications | Direct down-conversion mixer architecture |
US7515012B2 (en) * | 2002-06-20 | 2009-04-07 | Alfred E. Mann Foundation For Scientific Research | System and method for automatic tuning of a magnetic field generator |
US6909886B2 (en) * | 2002-08-30 | 2005-06-21 | Microtune ( Texas), L.P. | Current driven polyphase filters and method of operation |
DE10242364A1 (en) | 2002-09-12 | 2004-03-25 | Infineon Technologies Ag | Phase-locked loop for frequency modulation of mobile radio transmitter, has correction signal produced in evaluation unit from control voltage and reference VCO gain supplied, and connected to input of charge pump |
US7420409B2 (en) * | 2002-10-30 | 2008-09-02 | Dsp Group Switzerland Ag | Phase locked loop demodulator with gain control |
US6788155B2 (en) * | 2002-12-31 | 2004-09-07 | Intel Corporation | Low gain phase-locked loop circuit |
TWI332208B (en) * | 2003-01-28 | 2010-10-21 | Tian Holdings Llc | Method and apparatus for generating wobble signal |
US7286844B1 (en) * | 2003-01-31 | 2007-10-23 | Bbn Technologies Corp. | Systems and methods for three dimensional antenna selection and power control in an Ad-Hoc wireless network |
JP3842227B2 (en) * | 2003-02-25 | 2006-11-08 | Necエレクトロニクス株式会社 | PLL frequency synthesizer and its oscillation frequency selection method |
US7109763B1 (en) * | 2003-03-26 | 2006-09-19 | Cypress Semiconductor, Corp. | Phase locked loop operable over a wide frequency range |
US20040214543A1 (en) * | 2003-04-28 | 2004-10-28 | Yasuo Osone | Variable capacitor system, microswitch and transmitter-receiver |
US20040246039A1 (en) * | 2003-06-03 | 2004-12-09 | Chi-Ming Hsiao | Switched capacitor circuit capable of minimizing clock feedthrough effect in a voltage controlled oscillator circuit |
CN100379157C (en) * | 2003-06-24 | 2008-04-02 | 松下电器产业株式会社 | High frequency receiving device, integrated circuit used for same, and TV receiver using them |
US7162655B2 (en) * | 2003-07-16 | 2007-01-09 | Dell Products, L.P. | Method and system for information handling system power control |
KR100523802B1 (en) * | 2003-08-11 | 2005-10-25 | 학교법인 한국정보통신학원 | Source-Injection Parallel Coupled LC-Quadrature Voltage Controlled Oscillator |
DE10338092A1 (en) * | 2003-08-19 | 2005-04-21 | Infineon Technologies Ag | Method and device for driving an oscillator |
KR100531004B1 (en) * | 2003-08-25 | 2005-11-28 | 학교법인 한국정보통신학원 | Low Power Quadrature using Back-gate |
US7046093B1 (en) | 2003-08-27 | 2006-05-16 | Intergrated Device Technology, Inc. | Dynamic phase-locked loop circuits and methods of operation thereof |
US7224951B1 (en) * | 2003-09-11 | 2007-05-29 | Xilinx, Inc. | PMA RX in coarse loop for high speed sampling |
US7064618B2 (en) * | 2003-09-29 | 2006-06-20 | Intel Corporation | PLL with swappable tuning loops |
US7542437B1 (en) | 2003-10-02 | 2009-06-02 | Bbn Technologies Corp. | Systems and methods for conserving energy in a communications network |
US7038552B2 (en) * | 2003-10-07 | 2006-05-02 | Analog Devices, Inc. | Voltage controlled oscillator having improved phase noise |
WO2005041415A1 (en) * | 2003-10-23 | 2005-05-06 | Telefonaktiebolaget Lm Ericsson (Publ) | A multiband pll arrangement and a method of controlling such arrangement |
US7277518B2 (en) * | 2003-11-20 | 2007-10-02 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Low-jitter charge-pump phase-locked loop |
GB2409383B (en) * | 2003-12-17 | 2006-06-21 | Wolfson Ltd | Clock synchroniser |
US7609118B1 (en) | 2003-12-29 | 2009-10-27 | Sequoia Communications | Phase-locked loop calibration system |
US7496338B1 (en) | 2003-12-29 | 2009-02-24 | Sequoia Communications | Multi-segment gain control system |
US7551892B1 (en) | 2004-02-26 | 2009-06-23 | Bbn Technologies Corp | Low-power ad hoc network entry |
TWI351817B (en) | 2004-03-22 | 2011-11-01 | Integrated Device Tech | Transconductance and current modulation for resona |
US7504899B2 (en) * | 2004-03-22 | 2009-03-17 | Mobius Microsystems, Inc. | Inductor and capacitor-based clock generator and timing/frequency reference |
US7450659B2 (en) * | 2004-03-29 | 2008-11-11 | Agilent Technologies, Inc. | Digital modulator employing a polyphase up-converter structure |
US20050220224A1 (en) * | 2004-03-31 | 2005-10-06 | Silicon Laboratories Inc. | Polyphase filter with passband compensation and method therefor |
US7747237B2 (en) * | 2004-04-09 | 2010-06-29 | Skyworks Solutions, Inc. | High agility frequency synthesizer phase-locked loop |
CN1943114A (en) * | 2004-04-15 | 2007-04-04 | 皇家飞利浦电子股份有限公司 | Phase locked loop circuit |
US7522017B1 (en) | 2004-04-21 | 2009-04-21 | Sequoia Communications | High-Q integrated RF filters |
JP2005311945A (en) * | 2004-04-26 | 2005-11-04 | Matsushita Electric Ind Co Ltd | Pll circuit, radio communication device, and oscillation frequency control method |
US7538596B2 (en) * | 2004-05-25 | 2009-05-26 | Silicon Laboratories, Inc. | Low distortion quadrature mixer and method therefor |
US7053683B2 (en) * | 2004-05-27 | 2006-05-30 | Agere Systems Inc. | Voltage controlled oscillator with automatic band selector |
US7672648B1 (en) | 2004-06-26 | 2010-03-02 | Quintics Holdings | System for linear amplitude modulation |
US10369362B2 (en) * | 2004-06-28 | 2019-08-06 | The Alfred E. Mann Foundation For Scientific Research | Neural prosthetic with touch-like sensing |
US7339420B2 (en) * | 2004-07-27 | 2008-03-04 | Matsushita Electric Industrial Co., Ltd. | Method of switching PLL characteristics and PLL circuit |
JP2006086740A (en) * | 2004-09-15 | 2006-03-30 | Matsushita Electric Ind Co Ltd | Voltage controlled oscillator and semiconductor integrated circuit for communication |
WO2006087507A1 (en) * | 2004-09-20 | 2006-08-24 | Frontier Silicon Limited | Digital audio broadcast receiver |
CN101032073B (en) * | 2004-09-30 | 2011-09-28 | Nxp股份有限公司 | Frequency-tunable oscillator arrangement |
JP3964426B2 (en) * | 2004-11-17 | 2007-08-22 | シャープ株式会社 | Oscillator, integrated circuit, communication device |
DE102004057186B4 (en) | 2004-11-26 | 2007-10-31 | Texas Instruments Deutschland Gmbh | PLL circuit with a voltage controlled oscillator |
CN100407570C (en) * | 2004-12-03 | 2008-07-30 | 北京大学 | Voltage controlled oscillator with wide frequency band |
US20060119443A1 (en) * | 2004-12-08 | 2006-06-08 | Via Technologies Inc. | Damping coefficient variation mechanism in a phase locked loop |
US20060119441A1 (en) * | 2004-12-08 | 2006-06-08 | Via Technologies, Inc. | Phase locked loop damping coefficient correction mechanism |
US20060119442A1 (en) * | 2004-12-08 | 2006-06-08 | Via Technologies, Inc. | System and method for optimizing phase locked loop damping coefficient |
US7330736B2 (en) | 2004-12-17 | 2008-02-12 | Bbn Technologies Corp. | Methods and apparatus for reduced energy communication in an ad hoc network |
US8145201B2 (en) * | 2004-12-17 | 2012-03-27 | Raytheon Bbn Technologies Corp. | Methods and apparatus for reduced energy communication in an ad hoc network |
US7142062B2 (en) * | 2004-12-30 | 2006-11-28 | Nokia Corporation | VCO center frequency tuning and limiting gain variation |
US7746181B1 (en) | 2005-01-28 | 2010-06-29 | Cypress Semiconductor Corporation | Circuit and method for extending the usable frequency range of a phase locked loop (PLL) |
US7548122B1 (en) | 2005-03-01 | 2009-06-16 | Sequoia Communications | PLL with switched parameters |
US7479815B1 (en) | 2005-03-01 | 2009-01-20 | Sequoia Communications | PLL with dual edge sensitivity |
US7675379B1 (en) | 2005-03-05 | 2010-03-09 | Quintics Holdings | Linear wideband phase modulation system |
EP1861931A4 (en) * | 2005-03-11 | 2008-05-14 | Rfstream America Inc | A wideband tuning circuit |
US20080309827A1 (en) * | 2005-03-21 | 2008-12-18 | Nxp B.V. | Filter Device, Circuit Arrangement Comprising Such Filter Device as Well as Method of Operating Such Filter Device |
TWI387208B (en) * | 2005-03-21 | 2013-02-21 | Integrated Device Tech | Low-latency start-up for a monolithic clock generator and timing/frequency reference |
US7595626B1 (en) | 2005-05-05 | 2009-09-29 | Sequoia Communications | System for matched and isolated references |
US7479768B1 (en) * | 2005-05-26 | 2009-01-20 | National Semiconductor Corporation | System and method for providing variable gain loop control for use in adaptive voltage scaling |
US7772934B2 (en) * | 2005-09-14 | 2010-08-10 | Silicon Laboratories Inc. | Calibration of phase locked loop parameters based on static band information |
US20070070983A1 (en) * | 2005-09-28 | 2007-03-29 | Bbn Technologies Corp. | Methods and apparatus for improved efficiency communication |
US7342465B2 (en) * | 2005-10-20 | 2008-03-11 | Honeywell International Inc. | Voltage-controlled oscillator with stable gain over a wide frequency range |
US7812679B2 (en) * | 2005-11-29 | 2010-10-12 | Motorola, Inc. | Multi-band frequency generation method and apparatus |
US20070120616A1 (en) * | 2005-11-29 | 2007-05-31 | Gonzalez Armando J | Multi-band frequency generation method and apparatus |
WO2007085003A2 (en) * | 2006-01-20 | 2007-07-26 | Sirf Technology, Inc. | Method of eliminating temperature induced band switching in ultra wideband voltage controlled oscillator |
US7342460B2 (en) * | 2006-01-30 | 2008-03-11 | Silicon Laboratories Inc. | Expanded pull range for a voltage controlled clock synthesizer |
WO2007088595A1 (en) * | 2006-01-31 | 2007-08-09 | Fujitsu Limited | Pll circuit and semiconductor integrated device |
US7907037B2 (en) * | 2006-02-04 | 2011-03-15 | Evigia Systems, Inc. | Micro-electro-mechanical module |
US20070188255A1 (en) * | 2006-02-10 | 2007-08-16 | Roland Strandberg | Oscillator gain equalization |
US20070205200A1 (en) * | 2006-03-02 | 2007-09-06 | Brain Box Concepts | Soap bar holder and method of supporting a soap bar |
US7772930B2 (en) * | 2006-04-06 | 2010-08-10 | Broadcom Corporation | Calibration techniques for phase-locked loop bandwidth |
US7974374B2 (en) | 2006-05-16 | 2011-07-05 | Quintic Holdings | Multi-mode VCO for direct FM systems |
CN100466475C (en) * | 2006-06-01 | 2009-03-04 | 张海清 | Automatic regulating method and circuit for phase locking loop frequency synthesizer switch capacitor |
US7522005B1 (en) | 2006-07-28 | 2009-04-21 | Sequoia Communications | KFM frequency tracking system using an analog correlator |
US7679468B1 (en) | 2006-07-28 | 2010-03-16 | Quintic Holdings | KFM frequency tracking system using a digital correlator |
US7894545B1 (en) | 2006-08-14 | 2011-02-22 | Quintic Holdings | Time alignment of polar transmitter |
US8149733B2 (en) * | 2006-08-25 | 2012-04-03 | Raytheon Bbn Technologies Corp. | Systems and methods for synchronizing communication networks |
DE102006041804B4 (en) * | 2006-09-06 | 2014-04-03 | Infineon Technologies Ag | Phase-locked loop |
US7920033B1 (en) | 2006-09-28 | 2011-04-05 | Groe John B | Systems and methods for frequency modulation adjustment |
KR100847686B1 (en) * | 2006-10-12 | 2008-07-23 | (주)에프씨아이 | Phase Locked Loop having continuous bank calibration unit and method to prevent unlocking PLL |
US8139159B2 (en) * | 2006-10-25 | 2012-03-20 | Mstar Semiconductor, Inc. | Single down-conversion television tuner |
US8139160B2 (en) * | 2006-10-25 | 2012-03-20 | Mstar Semiconductor, Inc. | Television tuner with double quadrature mixing architecture |
TWI346460B (en) * | 2006-10-31 | 2011-08-01 | Realtek Semiconductor Corp | A clock and data recovery circuit and a method for adjusting loop bandwidth used thereby |
US7724095B2 (en) * | 2006-12-04 | 2010-05-25 | Evstratov Leonid V | Floating DC-offset circuit for phase detector |
GB0626024D0 (en) * | 2006-12-29 | 2007-02-07 | Nokia Corp | Dynamically adjusted phase locked loop |
US7821350B2 (en) * | 2007-01-19 | 2010-10-26 | Qualcomm Incorporated | Methods and apparatus for dynamic frequency scaling of phase locked loops for microprocessors |
US7692497B2 (en) * | 2007-02-12 | 2010-04-06 | Analogix Semiconductor, Inc. | PLLS covering wide operating frequency ranges |
US7633347B2 (en) * | 2007-03-08 | 2009-12-15 | 02Micro International Limited | Apparatus and method for operating a phase-locked loop circuit |
FI20075292A0 (en) * | 2007-04-26 | 2007-04-26 | Nokia Corp | Stabilization of oscillator signal |
US20080284530A1 (en) * | 2007-05-14 | 2008-11-20 | Stefano Pellerano | Phase noise minimized phase/frequency-locked voltage-controlled oscillator circuit |
US7675373B2 (en) * | 2007-05-29 | 2010-03-09 | Infineon Technologies Ag | Voltage controlled oscillator circuit and a method for configuring a voltage controlled oscillator circuit |
US7956695B1 (en) * | 2007-06-12 | 2011-06-07 | Altera Corporation | High-frequency low-gain ring VCO for clock-data recovery in high-speed serial interface of a programmable logic device |
US8149716B2 (en) | 2007-08-20 | 2012-04-03 | Raytheon Bbn Technologies Corp. | Systems and methods for adaptive routing in mobile ad-hoc networks and disruption tolerant networks |
US20090072911A1 (en) * | 2007-09-14 | 2009-03-19 | Ling-Wei Ke | Signal generating apparatus and method thereof |
US8044723B2 (en) * | 2007-09-14 | 2011-10-25 | Qualcomm Incorporated | Oscillator signal generation with spur mitigation in a wireless communication device |
US7921312B1 (en) | 2007-09-14 | 2011-04-05 | National Semiconductor Corporation | System and method for providing adaptive voltage scaling with multiple clock domains inside a single voltage domain |
US7609122B2 (en) * | 2007-10-05 | 2009-10-27 | Silicon Storage Technology, Inc. | Method and system for calibration of a tank circuit in a phase lock loop |
US7679457B2 (en) * | 2007-10-08 | 2010-03-16 | Advantest Corporation | Oscillating apparatus |
US8309685B2 (en) * | 2007-12-21 | 2012-11-13 | Celgene Avilomics Research, Inc. | HCV protease inhibitors and uses thereof |
TW200935719A (en) * | 2008-02-05 | 2009-08-16 | Rafael Microelectronics Inc | Multi-band VCO |
US20090315611A1 (en) * | 2008-06-24 | 2009-12-24 | Ralink Technology Corporation | Quadrature mixer circuit |
US20100001804A1 (en) * | 2008-07-06 | 2010-01-07 | Friend David M | System to improve a voltage-controlled oscillator and associated methods |
TW201012074A (en) * | 2008-09-15 | 2010-03-16 | Sunplus Technology Co Ltd | Frequency synthesis system with self-calibrated loop stability and bandwidth |
US8044724B2 (en) * | 2008-09-22 | 2011-10-25 | Mosys, Inc. | Low jitter large frequency tuning LC PLL for multi-speed clocking applications |
US8299862B1 (en) * | 2009-12-02 | 2012-10-30 | Marvell International Ltd. | Tuning circuit for inductor capacitor (LC) tank digitally controlled oscillator |
US8274317B2 (en) * | 2009-12-21 | 2012-09-25 | Electronics And Telecommunications Research Institute | Phase-locked loop circuit comprising voltage-controlled oscillator having variable gain |
US20110299644A1 (en) * | 2010-06-08 | 2011-12-08 | Bing Xu | Emission Suppression for Wireless Communication Devices |
TWI548202B (en) * | 2010-10-21 | 2016-09-01 | 南洋理工大學 | Integrated circuit architecture with strongly coupled lc tanks |
CN101986568B (en) * | 2010-10-22 | 2012-11-14 | 江苏锦丰电子有限公司 | Steady state phase-locking error-free phase locking system and phase locking method |
US8362843B2 (en) * | 2010-12-17 | 2013-01-29 | Qualcomm Incorporated | Method and apparatus for multi-point calibration for synthesizing varying frequency signals |
TWI427933B (en) * | 2011-03-18 | 2014-02-21 | Realtek Semiconductor Corp | Device and method for a feedback control of switch capacitive regulator |
US8456244B2 (en) | 2011-05-03 | 2013-06-04 | Skyworks Solutions, Inc. | Apparatus and methods for adjusting voltage controlled oscillator gain |
US8508308B2 (en) * | 2011-09-01 | 2013-08-13 | Lsi Corporation | Automatic frequency calibration of a multi-LCVCO phase locked loop with adaptive thresholds and programmable center control voltage |
US8610479B2 (en) * | 2011-10-18 | 2013-12-17 | Parade Technologies, Ltd. | On die low power high accuracy reference clock generation |
US8531245B2 (en) * | 2011-10-28 | 2013-09-10 | St-Ericsson Sa | Temperature compensation in a PLL |
US8816729B2 (en) * | 2011-11-14 | 2014-08-26 | Rockwell Automation Technologies, Inc. | Phase-locked-loop with quadrature tracking filter for synchronizing an electric grid |
US8704571B2 (en) * | 2011-11-14 | 2014-04-22 | Rockwell Automation Technologies, Inc. | Phase-locked-loop with quadrature tracking filter for synchronizing an electric grid |
US9225562B2 (en) | 2012-02-27 | 2015-12-29 | Intel Deutschland Gmbh | Digital wideband closed loop phase modulator with modulation gain calibration |
KR101931256B1 (en) | 2012-07-25 | 2018-12-20 | 삼성전자주식회사 | Wireless power reception apparatus and method |
US8872556B1 (en) * | 2013-04-30 | 2014-10-28 | Micrel, Inc. | PLL frequency synthesizer with multi-curve VCO implementing closed loop curve searching using charge pump current modulation |
US9030241B2 (en) | 2013-04-30 | 2015-05-12 | Micrel, Inc. | PLL frequency synthesizer with multi-curve VCO implementing closed loop curve searching |
KR20150073391A (en) | 2013-12-23 | 2015-07-01 | 삼성전자주식회사 | Voltage controlled oscillator and phase locked loop including the same |
US9425736B2 (en) | 2014-01-02 | 2016-08-23 | International Business Machines Corporation | Variable capacitor structure |
US9917507B2 (en) | 2015-05-28 | 2018-03-13 | Sandisk Technologies Llc | Dynamic clock period modulation scheme for variable charge pump load currents |
US10707905B2 (en) * | 2015-06-23 | 2020-07-07 | Skyworks Solutions, Inc. | Wideband multiplexer for radio-frequency applications |
US9503107B1 (en) * | 2015-07-27 | 2016-11-22 | Qualcomm Incorporated | Closed loop bank selection for temperature compensation in wireless systems |
US9647536B2 (en) | 2015-07-28 | 2017-05-09 | Sandisk Technologies Llc | High voltage generation using low voltage devices |
US9906227B2 (en) * | 2015-08-13 | 2018-02-27 | Maxlinear, Inc. | Method and system for a sampled loop filter in a phase locked loop (PLL) |
US9520776B1 (en) | 2015-09-18 | 2016-12-13 | Sandisk Technologies Llc | Selective body bias for charge pump transfer switches |
US9503100B1 (en) * | 2015-10-30 | 2016-11-22 | Texas Instruments Incorporated | Digitally reconfigurable ultra-high precision internal oscillator |
US9906230B2 (en) * | 2016-04-14 | 2018-02-27 | Huawei Technologies Co., Ltd. | PLL system and method of operating same |
US9966965B2 (en) * | 2016-06-10 | 2018-05-08 | Silicon Laboratories Inc. | Apparatus for low power signal generator and associated methods |
WO2018021788A1 (en) * | 2016-07-28 | 2018-02-01 | 엘지전자 주식회사 | Vehicle communication apparatus, and vehicle |
US10779140B2 (en) | 2016-07-28 | 2020-09-15 | Lg Electronics Inc. | Vehicle communication apparatus and vehicle |
US11804846B2 (en) * | 2018-11-05 | 2023-10-31 | Cadence Design Systems, Inc. | Phase-locked loop with phase information multiplication |
US11012079B1 (en) * | 2019-12-19 | 2021-05-18 | Bae Systems Information And Electronic Systems Integration Inc. | Continuous tuning of digitally switched voltage-controlled oscillator frequency bands |
CN113534883B (en) * | 2021-04-26 | 2022-10-25 | 西安交通大学 | Charge pump circuit with current source and compensation function |
Family Cites Families (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1591364B1 (en) | 1967-04-29 | 1970-08-20 | Philips Patentverwaltung | Circuit arrangement for tuning |
US3528859A (en) * | 1967-10-05 | 1970-09-15 | Hooker Chemical Corp | Electrode structure for wicking type fuel cell |
US3538450A (en) | 1968-11-04 | 1970-11-03 | Collins Radio Co | Phase locked loop with digital capacitor and varactor tuned oscillator |
US4568888A (en) * | 1983-11-08 | 1986-02-04 | Trw Inc. | PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction |
US4566888A (en) * | 1984-07-27 | 1986-01-28 | Ppg Industries, Inc. | Bushing construction |
US5126692A (en) * | 1987-08-03 | 1992-06-30 | Western Digital Corporation | Variable frequency system having linear combination of charge pump and voltage controlled oscillator |
US6714983B1 (en) | 1989-04-14 | 2004-03-30 | Broadcom Corporation | Modular, portable data processing terminal for use in a communication network |
US5091304A (en) * | 1989-08-21 | 1992-02-25 | International Technidyne Corporation | Whole blood activated partial thromboplastin time test and associated apparatus |
US4970472A (en) * | 1989-09-01 | 1990-11-13 | Delco Electronics Corporation | Compensated phase locked loop circuit |
US5682379A (en) | 1993-12-23 | 1997-10-28 | Norand Corporation | Wireless personal local area network |
US6359872B1 (en) | 1997-10-28 | 2002-03-19 | Intermec Ip Corp. | Wireless personal local area network |
US5030926A (en) | 1990-07-10 | 1991-07-09 | At&T Bell Laboratories | Voltage controlled balanced crystal oscillator circuit |
US5254958A (en) | 1991-02-19 | 1993-10-19 | Pacific Communications, Inc. | Phase-lock-loop circuit and method for compensating, data bias in the same |
US6374311B1 (en) | 1991-10-01 | 2002-04-16 | Intermec Ip Corp. | Communication network having a plurality of bridging nodes which transmit a beacon to terminal nodes in power saving state that it has messages awaiting delivery |
US5121085A (en) * | 1991-06-28 | 1992-06-09 | Digital Equipment Corporation | Dual-charge-pump bandwidth-switched phase-locked loop |
US5369376A (en) | 1991-11-29 | 1994-11-29 | Standard Microsystems, Inc. | Programmable phase locked loop circuit and method of programming same |
US5396376A (en) * | 1992-03-23 | 1995-03-07 | Conner Peripherals, Inc. | Multi-track embedded servo recording format and method |
US5254968A (en) * | 1992-06-15 | 1993-10-19 | General Motors Corporation | Electrically conductive plastic speed control resistor for an automotive blower motor |
US5315270A (en) * | 1992-08-28 | 1994-05-24 | At&T Bell Laboratories | Phase-locked loop system with compensation for data-transition-dependent variations in loop gain |
US5362990A (en) | 1993-06-02 | 1994-11-08 | Motorola, Inc. | Charge pump with a programmable pump current and system |
JP2778421B2 (en) | 1993-09-07 | 1998-07-23 | 日本電気株式会社 | Charge pump type phase locked loop |
US5483125A (en) * | 1993-12-06 | 1996-01-09 | General Electric Company | Ballast circuit for a gas discharge lamp having a cathode pre-heat arrangement |
US5485126A (en) * | 1994-01-25 | 1996-01-16 | International Business Machines Corporation | Ring oscillator circuit having output with fifty percent duty cycle |
FR2717019A1 (en) | 1994-03-02 | 1995-09-08 | Philips Composants | Oscillator device locked in phase. |
JPH0879074A (en) * | 1994-09-05 | 1996-03-22 | Mitsubishi Electric Corp | Phase locked loop circuit |
FI97578C (en) * | 1994-10-14 | 1997-01-10 | Nokia Telecommunications Oy | Synthesizer lockout alarm switching |
EP0822187A4 (en) * | 1995-02-07 | 1998-05-13 | Nissan Chemical Ind Ltd | Pyrazole derivatives and herbicides |
US5563553A (en) * | 1995-08-15 | 1996-10-08 | Sigmatel Inc. | Method and apparatus for a controlled oscillation that may be used in a phase locked loop |
JPH09162730A (en) | 1995-11-29 | 1997-06-20 | Internatl Business Mach Corp <Ibm> | Pll circuit |
JP2845185B2 (en) * | 1995-11-29 | 1999-01-13 | 日本電気株式会社 | PLL circuit |
US5563563A (en) * | 1995-12-04 | 1996-10-08 | Ford Motor Company | Solenoid with an improved contact design and a system utilizing the solenoid |
US5648744A (en) | 1995-12-22 | 1997-07-15 | Microtune, Inc. | System and method for voltage controlled oscillator automatic band selection |
US5739730A (en) | 1995-12-22 | 1998-04-14 | Microtune, Inc. | Voltage controlled oscillator band switching technique |
US5625325A (en) * | 1995-12-22 | 1997-04-29 | Microtune, Inc. | System and method for phase lock loop gain stabilization |
US5748050A (en) * | 1996-03-29 | 1998-05-05 | Symbios Logic Inc. | Linearization method and apparatus for voltage controlled oscillator |
US6028488A (en) * | 1996-11-08 | 2000-02-22 | Texas Instruments Incorporated | Digitally-controlled oscillator with switched-capacitor frequency selection |
US6137372A (en) * | 1998-05-29 | 2000-10-24 | Silicon Laboratories Inc. | Method and apparatus for providing coarse and fine tuning control for synthesizing high-frequency signals for wireless communications |
US6126692A (en) * | 1998-06-25 | 2000-10-03 | New York Society For The Relief Of The Ruptured And Crippled Maintaining The Hospital For Special Surgery | Retaining mechanism for a modular tibial component of a knee prosthesis |
KR100272170B1 (en) * | 1998-08-17 | 2000-11-15 | 윤종용 | Wide range vco and pll using the same |
US6188900B1 (en) * | 1998-08-31 | 2001-02-13 | Texas Instruments Incorporated | Mobile device assisted handoff system for code division multiple access and wideband code division multiple access networks |
US6091304A (en) | 1998-09-22 | 2000-07-18 | Lg Information & Communications, Ltd. | Frequency band select phase lock loop device |
US6163184A (en) | 1998-12-09 | 2000-12-19 | Lucent Technologies, Inc. | Phase locked loop (PLL) circuit |
US6211745B1 (en) * | 1999-05-03 | 2001-04-03 | Silicon Wave, Inc. | Method and apparatus for digitally controlling the capacitance of an integrated circuit device using mos-field effect transistors |
DE19934723A1 (en) | 1999-07-23 | 2001-02-01 | Infineon Technologies Ag | Controllable current source circuit and phase locked loop equipped therewith |
US6133797A (en) * | 1999-07-30 | 2000-10-17 | Motorola, Inc. | Self calibrating VCO correction circuit and method of operation |
US6424825B1 (en) * | 1999-11-16 | 2002-07-23 | Motorola, Inc. | Feedforward and feedback control in a radio |
US6478667B2 (en) * | 2000-01-28 | 2002-11-12 | Excel Corporation | Method and apparatus for tenderizing meat |
JP2002025292A (en) * | 2000-07-11 | 2002-01-25 | Hitachi Ltd | Semiconductor integrated circuit |
US6680653B2 (en) * | 2000-09-29 | 2004-01-20 | Skyworks Solutions, Inc. | VCO tuning curve compensated charge pump current synthesizer |
US6462594B1 (en) * | 2000-11-08 | 2002-10-08 | Xilinx, Inc. | Digitally programmable phase-lock loop for high-speed data communications |
US6583675B2 (en) * | 2001-03-20 | 2003-06-24 | Broadcom Corporation | Apparatus and method for phase lock loop gain control using unit current sources |
DE10126134B4 (en) * | 2001-05-29 | 2004-02-26 | W.E.T. Automotive Systems Ag | Flat heating element |
US6608511B1 (en) * | 2002-07-17 | 2003-08-19 | Via Technologies, Inc. | Charge-pump phase-locked loop circuit with charge calibration |
JP3842227B2 (en) * | 2003-02-25 | 2006-11-08 | Necエレクトロニクス株式会社 | PLL frequency synthesizer and its oscillation frequency selection method |
TW591770B (en) * | 2003-03-14 | 2004-06-11 | Ind Tech Res Inst | Packaging method for semiconductor device |
US7012471B2 (en) * | 2003-06-27 | 2006-03-14 | Analog Devices, Inc. | Gain compensated fractional-N phase lock loop system and method |
US6891414B1 (en) * | 2004-03-05 | 2005-05-10 | Rf Micro Devices, Inc. | Digital calibration for capacitor voltage non-linearity |
-
2001
- 2001-03-20 US US09/811,611 patent/US6583675B2/en not_active Expired - Lifetime
-
2002
- 2002-03-20 AT AT02252014T patent/ATE363155T1/en not_active IP Right Cessation
- 2002-03-20 DE DE60220209T patent/DE60220209T2/en not_active Expired - Lifetime
- 2002-03-20 EP EP05013611A patent/EP1592135A1/en not_active Withdrawn
- 2002-03-20 EP EP02252014A patent/EP1244215B1/en not_active Expired - Lifetime
-
2003
- 2003-05-23 US US10/443,741 patent/US6838947B2/en not_active Expired - Lifetime
-
2004
- 2004-12-23 US US11/019,451 patent/US7129792B2/en not_active Expired - Lifetime
-
2005
- 2005-03-30 US US11/096,154 patent/US7119624B2/en not_active Expired - Lifetime
- 2005-03-31 US US11/095,117 patent/US7355485B2/en not_active Expired - Lifetime
- 2005-12-21 US US11/314,618 patent/US7224234B2/en not_active Expired - Lifetime
- 2005-12-21 US US11/313,372 patent/US7443248B2/en not_active Expired - Fee Related
-
2006
- 2006-07-21 US US11/459,205 patent/US7271667B2/en not_active Expired - Lifetime
- 2006-09-25 US US11/534,870 patent/US7239212B2/en not_active Expired - Lifetime
-
2007
- 2007-05-29 US US11/754,804 patent/US7449963B2/en not_active Expired - Fee Related
- 2007-06-25 US US11/767,899 patent/US7397319B2/en not_active Expired - Lifetime
-
2008
- 2008-03-25 US US12/054,755 patent/US7528666B2/en not_active Expired - Fee Related
- 2008-10-28 US US12/259,770 patent/US7948325B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7239212B2 (en) | 2007-07-03 |
US20060097796A1 (en) | 2006-05-11 |
US7224234B2 (en) | 2007-05-29 |
US7271667B2 (en) | 2007-09-18 |
US20020135428A1 (en) | 2002-09-26 |
US20080174361A1 (en) | 2008-07-24 |
US7129792B2 (en) | 2006-10-31 |
US7397319B2 (en) | 2008-07-08 |
US7443248B2 (en) | 2008-10-28 |
DE60220209T2 (en) | 2008-01-17 |
US20030206065A1 (en) | 2003-11-06 |
EP1244215A1 (en) | 2002-09-25 |
US7948325B2 (en) | 2011-05-24 |
US20050174186A1 (en) | 2005-08-11 |
US20050168297A1 (en) | 2005-08-04 |
US20060097797A1 (en) | 2006-05-11 |
US20090058536A1 (en) | 2009-03-05 |
US7449963B2 (en) | 2008-11-11 |
US20050104677A1 (en) | 2005-05-19 |
EP1592135A1 (en) | 2005-11-02 |
US20070018747A1 (en) | 2007-01-25 |
US7119624B2 (en) | 2006-10-10 |
US20070247238A1 (en) | 2007-10-25 |
US20070268076A1 (en) | 2007-11-22 |
DE60220209D1 (en) | 2007-07-05 |
US7355485B2 (en) | 2008-04-08 |
US7528666B2 (en) | 2009-05-05 |
US6583675B2 (en) | 2003-06-24 |
US20060284689A1 (en) | 2006-12-21 |
ATE363155T1 (en) | 2007-06-15 |
US6838947B2 (en) | 2005-01-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP1244215B1 (en) | Phase lock loop gain control using unit current sources | |
US8564340B2 (en) | Dual phase-locked loop circuit and method for controlling the same | |
US6985044B2 (en) | Varactor folding technique for phase noise reduction in electronic oscillators | |
US6683509B2 (en) | Voltage controlled oscillators | |
US7573347B2 (en) | Digitally controlled oscillator device and method for generating an oscillating signal with a digitally controlled phase locked loop | |
US7432768B2 (en) | Voltage controlled digital analog oscillator and frequency synthesizer using the same | |
JP2010501155A (en) | Continuous gain compensation and fast band selection in a multistandard multifrequency synthesizer. | |
US20040090278A1 (en) | Voltage-controlled oscillator and integrated circuit device provided with it | |
US7098752B2 (en) | Circuit arrangement for generating a reference current and oscillator circuit having the circuit arrangement | |
EP0270298B1 (en) | Wide range oscillator | |
CN115349227A (en) | Phase-locked loop |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
AX | Request for extension of the european patent |
Free format text: AL;LT;LV;MK;RO;SI |
|
17P | Request for examination filed |
Effective date: 20030227 |
|
AKX | Designation fees paid |
Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
17Q | First examination report despatched |
Effective date: 20050310 |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CH Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 Ref country code: LI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 |
|
RAP1 | Party data changed (applicant data changed or rights of an application transferred) |
Owner name: BROADCOM CORPORATION |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: FG4D |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
REF | Corresponds to: |
Ref document number: 60220209 Country of ref document: DE Date of ref document: 20070705 Kind code of ref document: P |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070823 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070903 |
|
NLV1 | Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act | ||
ET | Fr: translation filed | ||
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20071023 Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed |
Effective date: 20080226 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070824 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20080331 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20080320 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CY Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20080320 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: TR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20070523 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 14 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 15 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 60220209 Country of ref document: DE Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, DE Ref country code: DE Ref legal event code: R081 Ref document number: 60220209 Country of ref document: DE Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LT, SG Free format text: FORMER OWNER: BROADCOM CORP., IRVINE, CALIF., US Ref country code: DE Ref legal event code: R081 Ref document number: 60220209 Country of ref document: DE Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE., SG Free format text: FORMER OWNER: BROADCOM CORP., IRVINE, CALIF., US |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 16 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20171005 AND 20171011 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: PLFP Year of fee payment: 17 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: TP Owner name: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD., SG Effective date: 20180228 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R082 Ref document number: 60220209 Country of ref document: DE Representative=s name: BOSCH JEHLE PATENTANWALTSGESELLSCHAFT MBH, DE Ref country code: DE Ref legal event code: R081 Ref document number: 60220209 Country of ref document: DE Owner name: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LT, SG Free format text: FORMER OWNER: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE, SG |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 732E Free format text: REGISTERED BETWEEN 20190222 AND 20190227 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20200327 Year of fee payment: 19 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20200325 Year of fee payment: 19 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20210310 Year of fee payment: 20 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20210320 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210331 Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20210320 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R071 Ref document number: 60220209 Country of ref document: DE |