US20090116593A1 - Circuit for providing automatic adaptation to frequency offsets in high speed serial links - Google Patents
Circuit for providing automatic adaptation to frequency offsets in high speed serial links Download PDFInfo
- Publication number
- US20090116593A1 US20090116593A1 US12/349,385 US34938509A US2009116593A1 US 20090116593 A1 US20090116593 A1 US 20090116593A1 US 34938509 A US34938509 A US 34938509A US 2009116593 A1 US2009116593 A1 US 2009116593A1
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- United States
- Prior art keywords
- rotate
- phase
- circuit
- down signals
- adjusts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0063—Elements of loops
- H04L2027/0065—Frequency error detectors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0063—Elements of loops
- H04L2027/0067—Phase error detectors
Definitions
- the present invention relates to providing automatic adaptation to frequency offsets in high speed serial links.
- serializer In order for high-speed serial transmission to occur, the digital data signal from inside the computer must be transformed from the parallel format into a serial format prior to transmission of the data over the serial communication link. This transformation is generally accomplished by processing the computer's internal data signal through a piece of computer equipment known as a serial link transmitter or “serializer.”
- the function of the serializer is to receive a parallel data stream as input and, by manipulating the parallel data stream, output a serial form of the data capable of high-speed transmission over a suitable communication link.
- a piece of computer equipment known as a “deserializer” is employed to convert the incoming data from the serial format to a parallel format for use within the destination computer system.
- a frequency offset can occur between the frequency of the data coming in and the reference clock. Any frequency offset between the transmitter and receiver of a link pair causes the clock-data-recovery (CDR) loop to chase the optimum sampling point with some delay.
- CDR clock-data-recovery
- First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts.
- An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver.
- An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments.
- Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
- FIG. 1 illustrates a block diagram of an example embodiment of a phase rotator control adjustment circuit of logic components in accordance with the present invention.
- FIG. 2 illustrates a logic table for generating new rotate down (Rot_dn_) and rotate up (Rot_up_) signals by the circuit of FIG. 1 .
- FIG. 3 illustrates pseudo-code simulating the operation of a quarter-rate version of the circuit of FIG. 1 .
- FIG. 4 illustrates a block diagram of a receiver link including the circuit of FIG. 1 .
- the present invention relates to providing automatic adaptation to frequency offsets in high speed serial links.
- the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
- Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art.
- the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
- phase rotators are used to adjust the phase based on the frequency offset.
- the phase rotator receives a rotate up or rotate down signal based on early or late edge detections and then either rotates the phase up or rotates the phase down accordingly.
- the present invention monitors the rotate up and rotate down signal to determine how well the phase is being monitored. The monitoring information is used to predict a trend of movement in a particular direction by the circuit and cancel out the offset proactively based on the detected trend.
- FIG. 1 illustrates a block diagram of an example embodiment of a phase rotator control adjustment circuit 8 of logic components to perform the monitoring in accordance with the present invention.
- rotate down (Rot_dn) and rotate up (Rot_up) signals from a phase rotator control are input into an up/down counter 10 .
- a chosen number of bits from the input signal are used for averaging, i.e., to determine how big a difference in the ups/downs is seen before the remaining bits of the input signal are added by an accumulator 12 .
- 3 LSBs (least significant bits) of the received data are used for averaging, while 11 MSBs (most significant bits) are accumulated.
- the underflow and overflow states of the accumulator 12 are input to combinatorial logic 14 , along with the Rot_dn and Rot_up signals. From the combinatorial logic 14 , new rotate down (Rot_dn_) and rotate up (Rot_up_) are generated, as indicated by the logic table of FIG. 2 .
- FIG. 3 illustrates pseudo-code simulating the operation of the circuit of FIG. 1 for a quarter-rate version.
- the process initiates by transforming the active circuitry for quarter-rate operation. A check is then made for early/late difference with a corresponding step in the counter of up or down. The counter data is averaged over the LSBs and the counter MSBs are added to the accumulator. A check of the overflow/underflow status of the accumulator and the rotate up and down signals occurs, as indicated, to generate the new rotate up and down signals as desired. In this manner, the overflow and underflow signals of the accumulator trigger_blind_phase steps at a constant rate; the rate increases until the up and down inputs are balanced.
- the operations of the receiver link occur as is standardly understood with a phase rotator that compensates for frequency offset.
- the resultant Rot_up_ and Rot_dn_ signals from the phase rotator adjustment circuitry of the present invention reduces jitter and allows handling of much larger offsets when implemented in a receiver link, such as that shown in FIG. 4 .
- a differential signal is received in a receiver 20 that passes the data to latches 22 and 24 and then to memory 26 .
- the data from memory 26 is output to a shift register 28 that is coupled to a rate counter 30 and 8/10 bit register 32 .
- the memory 26 is further coupled to XOR (exclusive-OR) logic 34 , which is used to generate early and late signals for a phase rotator control 36 .
- the Rot_up and Rot_dn signals from the phase rotator control 36 are passed to an OR gate 38 and to the phase rotator control adjustment circuit 8 .
- the OR gate 38 logically combines the Rot_up and Rot_dn signal from control 36 with the Rot_up_ and Rot_dn_ from adjustment circuit 8 of the present invention as presented hereinabove and outputs the result to a phase rotator counter 40 .
- the counter 40 data passes through a thermometer code generator 42 and latches 44 before being received by a phase rotator 46 .
- a multi-phase half-rate PLL (phase-locked loop) 48 is also coupled to the phase rotator 46 .
- the data from the phase rotator 46 produces a logic clock signal and is fed back to the latches 22 , as shown.
Abstract
Description
- This application is a continuation application under 35 U.S.C. §120 and claims priority to U.S. patent application Ser. No. 10/791,175, filed Mar. 2, 2004, entitled, “Method for Providing Automatic Adaptation to Frequency Offsets in High Speed Serial Links,” all of which is incorporated herein by reference.
- The present invention relates to providing automatic adaptation to frequency offsets in high speed serial links.
- The ability to perform and achieve high speed transmissions of digital data has become expected in today's computing environment. In most cases, the transmission of digital data over longer distances is accomplished by sending the data in a high-speed serial format (i.e., one single bit after another) over a communication link designed to handle computer communications. In this fashion, data can be transferred from one computer system to another, even if the computer systems are geographically remote.
- In order for high-speed serial transmission to occur, the digital data signal from inside the computer must be transformed from the parallel format into a serial format prior to transmission of the data over the serial communication link. This transformation is generally accomplished by processing the computer's internal data signal through a piece of computer equipment known as a serial link transmitter or “serializer.” The function of the serializer is to receive a parallel data stream as input and, by manipulating the parallel data stream, output a serial form of the data capable of high-speed transmission over a suitable communication link. Once the serialized data has arrived at the desired destination, a piece of computer equipment known as a “deserializer” is employed to convert the incoming data from the serial format to a parallel format for use within the destination computer system.
- For high speed serializer/deserializer (HSS) link pairs, a frequency offset can occur between the frequency of the data coming in and the reference clock. Any frequency offset between the transmitter and receiver of a link pair causes the clock-data-recovery (CDR) loop to chase the optimum sampling point with some delay. The inability to track the offset accurately increases jitter and degrades the link performance, e.g., by increasing the bit error rate.
- Accordingly, a need exists for better compensation of frequency offset adjustment in a serial link transmitter/receiver pair. The present invention addresses such a need.
- Aspects of providing automatic adaptation to frequency offsets in high speed serial links are described. First signals for phase adjusts in a receiver link are adjusted by detecting trends in the first signals to generate second signals, the second signals improving a rate of compensation for the frequency offsets by the phase adjusts. An up/down counter is included for counting signals for phase adjustments by a clock-data-recovery loop of a serial receiver. An adder is coupled to the up/down counter and outputs accumulated data indicative of a trend in the phase adjustments. Combinatorial logic coupled to the adder adapts the signals based on the accumulated data.
-
FIG. 1 illustrates a block diagram of an example embodiment of a phase rotator control adjustment circuit of logic components in accordance with the present invention. -
FIG. 2 illustrates a logic table for generating new rotate down (Rot_dn_) and rotate up (Rot_up_) signals by the circuit ofFIG. 1 . -
FIG. 3 illustrates pseudo-code simulating the operation of a quarter-rate version of the circuit ofFIG. 1 . -
FIG. 4 illustrates a block diagram of a receiver link including the circuit ofFIG. 1 . - The present invention relates to providing automatic adaptation to frequency offsets in high speed serial links. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
- Typically, phase rotators are used to adjust the phase based on the frequency offset. The phase rotator receives a rotate up or rotate down signal based on early or late edge detections and then either rotates the phase up or rotates the phase down accordingly. The present invention monitors the rotate up and rotate down signal to determine how well the phase is being monitored. The monitoring information is used to predict a trend of movement in a particular direction by the circuit and cancel out the offset proactively based on the detected trend.
FIG. 1 illustrates a block diagram of an example embodiment of a phase rotatorcontrol adjustment circuit 8 of logic components to perform the monitoring in accordance with the present invention. - Referring now to
FIG. 1 , rotate down (Rot_dn) and rotate up (Rot_up) signals from a phase rotator control (not shown) are input into an up/downcounter 10. In a preferred embodiment, a chosen number of bits from the input signal are used for averaging, i.e., to determine how big a difference in the ups/downs is seen before the remaining bits of the input signal are added by anaccumulator 12. In the example shown, 3 LSBs (least significant bits) of the received data are used for averaging, while 11 MSBs (most significant bits) are accumulated. The underflow and overflow states of theaccumulator 12 are input tocombinatorial logic 14, along with the Rot_dn and Rot_up signals. From thecombinatorial logic 14, new rotate down (Rot_dn_) and rotate up (Rot_up_) are generated, as indicated by the logic table ofFIG. 2 . -
FIG. 3 illustrates pseudo-code simulating the operation of the circuit ofFIG. 1 for a quarter-rate version. As indicated, the process initiates by transforming the active circuitry for quarter-rate operation. A check is then made for early/late difference with a corresponding step in the counter of up or down. The counter data is averaged over the LSBs and the counter MSBs are added to the accumulator. A check of the overflow/underflow status of the accumulator and the rotate up and down signals occurs, as indicated, to generate the new rotate up and down signals as desired. In this manner, the overflow and underflow signals of the accumulator trigger_blind_phase steps at a constant rate; the rate increases until the up and down inputs are balanced. - It should be appreciated that the operations of the receiver link occur as is standardly understood with a phase rotator that compensates for frequency offset. However, the resultant Rot_up_ and Rot_dn_ signals from the phase rotator adjustment circuitry of the present invention reduces jitter and allows handling of much larger offsets when implemented in a receiver link, such as that shown in
FIG. 4 . Referring toFIG. 4 , a differential signal is received in areceiver 20 that passes the data to latches 22 and 24 and then tomemory 26. The data frommemory 26 is output to ashift register 28 that is coupled to arate counter bit register 32. Thememory 26 is further coupled to XOR (exclusive-OR)logic 34, which is used to generate early and late signals for aphase rotator control 36. The Rot_up and Rot_dn signals from thephase rotator control 36 are passed to anOR gate 38 and to the phase rotatorcontrol adjustment circuit 8. The ORgate 38 logically combines the Rot_up and Rot_dn signal fromcontrol 36 with the Rot_up_ and Rot_dn_ fromadjustment circuit 8 of the present invention as presented hereinabove and outputs the result to aphase rotator counter 40. As is commonly understood, thecounter 40 data passes through athermometer code generator 42 andlatches 44 before being received by aphase rotator 46. A multi-phase half-rate PLL (phase-locked loop) 48 is also coupled to thephase rotator 46. The data from thephase rotator 46 produces a logic clock signal and is fed back to thelatches 22, as shown. - Thus, with the inclusion of the present invention in an HSS link, a straightforward enhancement of serial links is achieved that provides an efficient and effective manner of better compensating for frequency offsets. Further, by monitoring the long term trends of phase adjusts created by the clock and data recovery circuit of the serial link, better adaptation of the phase adjustment occurs through creation of future adjusts based on the previous adjusts.
- From the foregoing, it will be observed that numerous variations and modifications may be effected without departing from the spirit and scope of the novel concept of the invention. It is to be understood that no limitation with respect to the specific methods and apparatus illustrated herein is intended or should be inferred. It is, of course, intended to cover by the appended claims all such modifications as fall within the scope of the claims.
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/349,385 US20090116593A1 (en) | 2004-03-02 | 2009-01-06 | Circuit for providing automatic adaptation to frequency offsets in high speed serial links |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/791,175 US7477713B2 (en) | 2004-03-02 | 2004-03-02 | method for providing automatic adaptation to frequency offsets in high speed serial links |
US12/349,385 US20090116593A1 (en) | 2004-03-02 | 2009-01-06 | Circuit for providing automatic adaptation to frequency offsets in high speed serial links |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US10/791,175 Continuation US7477713B2 (en) | 2004-03-02 | 2004-03-02 | method for providing automatic adaptation to frequency offsets in high speed serial links |
Publications (1)
Publication Number | Publication Date |
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US20090116593A1 true US20090116593A1 (en) | 2009-05-07 |
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ID=34911608
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US10/791,175 Expired - Fee Related US7477713B2 (en) | 2004-03-02 | 2004-03-02 | method for providing automatic adaptation to frequency offsets in high speed serial links |
US12/349,385 Abandoned US20090116593A1 (en) | 2004-03-02 | 2009-01-06 | Circuit for providing automatic adaptation to frequency offsets in high speed serial links |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US10/791,175 Expired - Fee Related US7477713B2 (en) | 2004-03-02 | 2004-03-02 | method for providing automatic adaptation to frequency offsets in high speed serial links |
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Country | Link |
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US (2) | US7477713B2 (en) |
TW (1) | TW200537812A (en) |
WO (1) | WO2005086351A1 (en) |
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US7085970B2 (en) | 2002-07-23 | 2006-08-01 | International Business Machines Corporation | Fast detection of incorrect sampling in an oversampling clock and data recovery system |
GB2520716A (en) * | 2013-11-28 | 2015-06-03 | Ibm | Clock recovery method and apparatus |
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Also Published As
Publication number | Publication date |
---|---|
WO2005086351A1 (en) | 2005-09-15 |
US20050195863A1 (en) | 2005-09-08 |
US7477713B2 (en) | 2009-01-13 |
TW200537812A (en) | 2005-11-16 |
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