US5457702A - Check bit code circuit for simultaneous single bit error correction and burst error detection - Google Patents
Check bit code circuit for simultaneous single bit error correction and burst error detection Download PDFInfo
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- US5457702A US5457702A US08/153,453 US15345393A US5457702A US 5457702 A US5457702 A US 5457702A US 15345393 A US15345393 A US 15345393A US 5457702 A US5457702 A US 5457702A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/43—Majority logic or threshold decoding
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/17—Burst error correction, e.g. error trapping, Fire codes
Definitions
- the present invention relates generally to digital error correction and detection schemes.
- it is a design for single bit error correction and burst (multiple bit) error detection in high speed digital memories.
- the error correction and detection process comprises: (1) check bits are regenerated from the received information bit; (2) syndrome bits are generated by comparing the regenerated check bits and the received check bits; (3) the syndrome bits are decoded to determine the erroneous location; and (4) the error correction is accomplished by complementing the erroneous bit located by decoding the syndrome.
- the prior art includes one-step majority decoding in conjunction with single and multiple error correction, and related coding and design. A discussion of this may be found in M. Y. Hsiao, D. C. Bossen and R. T. Chien, "Orthogonal Latin Square Codes", IBM J. RES. DEVELOP., pp. 390-394, July 1970, which is hereby incorporated herein by cross-reference.
- the prior art approach only accommodates a specific format arrangement of information unit (commonly referred to as "data word”). This specific format is characterized as having a data word size of "p" bits, and involving partitioning with a size of partition of m bits, where "m" is exactly the square root of p exactly the square root of p for purposes of single error processing.
- a still further object of the present invention is to provide a technique for optimal performance of error correction and detection which can provide optimal fault tolerance and yet be capable of providing such correction and detection quickly enough for use with modern high speed memories.
- a still further object is to provide the implementation of both error correction and detection employing one-step majority circuitry.
- a yet further object is to provide the implementation of a range of single error processing scenarios using a combination of self orthogonal and linear coding.
- a yet another objective is to provide a technique for optimal performance of correcting single bit error and detecting burst errors which may be implemented with the convenience of employing Application Specific Integrated Circuit (ASIC) computer aided design and production methods.
- ASIC Application Specific Integrated Circuit
- a design for an error corrector and detector (ECD) capable of correcting single bit errors and detecting burst errors.
- the design consists of two main features: one for error detection and one for error correction. These features operate in parallel such that the correction and detection phases may occur simultaneously.
- the error detection feature utilizes a single phase "exclusive-OR” (EOR) circuit to check each partition of the data for errors.
- the error correction feature uses a single phase “exclusive-OR” (EOR) circuit in combination with a single phase “voting" (majority) circuit to determine the correct value for each data bit.
- the outputs of the error detection circuit for each partition are combined to generate the error status signal output.
- a design is provided which utilizes the aforementioned error corrector and detector (ECD) in conjunction with existing high speed memories and a central processing unit (CPU) to provide a complete four cycle memory system.
- ECD error corrector and detector
- CPU central processing unit
- FIG. 1 is a block diagram of a CPU and memory system including the novel error corrector and detector of the present invention
- FIG. 1A is an H-parity matrix diagram (convention for representing data regeneration schemes) useful in describing the operation of the check bit generator of FIG. 1 in conjunction with a memory system employing a size of unit of data of 32 bits;
- FIG. 1B is an H parity matrix diagram employed in a prior art device
- FIG. 2 is a block diagram of the error corrector and detector (ECD) of FIG. 1, which block diagram is at a lower level (i.e., shows more detail) than that of FIG. 1;
- ECD error corrector and detector
- FIG. 3 is another type of matrix diagram (unique for purposes of describing the present invention) useful in describing the relationships between (i) partitioning of a data word in accordance with the present invention, (ii) the arrangement of binary digit values in the H-parity matrix of FIG. 1A, and (iii) certain exclusive-ORING circuitry;
- FIG. 4 is a block diagram of one of the error corrector modules of FIG. 2, which block diagram is at a still lower level;
- FIG. 5 is a block diagram at such still lower level of one of the error corrector and detector modules of FIG. 2;
- FIG. 6 is a block diagram at such still lower level of the error status module of FIG. 2;
- FIG. 7 is a diagrammatic depiction of a possible partitioning of the system of FIG. 1 into separate modules in connection with a very large scale integrated circuit (VLSI) chip implementation of the system.
- VLSI very large scale integrated circuit
- the decoder 12 which is coupled to the enable inputs of various other circuits, is a simple two input X/Y decoder implemented by a conventional logic network within the design capability of persons of skill in the art to generate four distinct cycles in the memory system: write, read(1), read(2), and diagnostic. In the vernacular of those skilled in the art the foregoing conventional logic network is sometimes referred to as "glue logic".
- the error correction and detection system 10 is not limited to memories having one particular size of information unit (commonly called "data word"). Given a size of data word of "p" bits, this data word is then subdivided into “n” partitions which contain "m” bits each. For example, in connection with the embodiment corresponding to the H-parity matrix (or simply "H-matrix”) of FIG. 1A, the size of data word p is thirty-two (32) bits (data bits d 0 through d 31 ), which is broken down into eight (8) partitions, n, each partition containing four (4) bits, m.
- data word p is thirty-two (32) bits (data bits d 0 through d 31 ), which is broken down into eight (8) partitions, n, each partition containing four (4) bits, m.
- An H-matrix is a conventional form of representation of a data regeneration scheme for data words. It will be appreciated that the H-matrix scheme in accordance with the present invention produces both error correction check bits and burst error check bits.
- the data for creating the check bits is permanently stored in the high speed memory 20 as "fixed, hard data", which shall hereinafter be called "check bit creating data”. Under control of a decoder 12 the check bit data is latched into a check bit generator 14.
- the check bits which are thusly generated are conventionally stored in memory 20 in operative association with corresponding inputted data words, so that error correction (i.e., data regeneration) and error detection functions can be performed when the data word is retrieved from memory 20.
- the positions of the matrix in the horizontal direction represent a series of data bit positions (d 0 , d 1 . . . d 31 ) and a series of check bit positions (C 0 , C 1 . . . C 11 ).
- the top row of the matrix is not part of the matrix. Instead it is a header row containing the identity of the bit position or check position of the column beneath. Beneath the header row are twelve (12) rows, which together with the bit position columns constitute the matrix's format.
- Each vertical position in a column is alternatively predeterminedly coded as a logical one ("1") position-depicted as a "1" in FIG.
- each partition, m is chosen such that m is the largest integer less than the square root of p which evenly divides p.
- the H-matrix of FIG. 1A includes vertically extending lines defining these partitions, namely the lines between subsets of bit positions d 0 . . . d 3 , d 4 . . . d 5 , . . . etc.
- check bit generator 14 for producing check bits based upon the aforesaid H-matrix generates an error correction code which is characterized both as linear and having the property of self orthogonality, and in the instant invention is further characterized as belonging to a subclass of self orthogonal codes which consists of all self orthogonal codes exclusive of Latin square codes (i.e., exclusive of the Latin square codes proposed in the hereinabove referenced article "Orthogonal Latin Square Codes" by M. Y. Hsiao et al in which the partition size m is exactly the square root of the data word bit length, p).
- This error correction code operatively interacts with the aforesaid format of the memory's information unit (or data word) as will be described.
- check bit creating data is read from a data input latch 22 into the check bit generator 14.
- the check bit generator 14 operatively coacts with the data in an operatively relationship in synchronism with the aforesaid partitioning of p bits of the information unit into n partitions each containing m bits.
- the first n check bits are set to logical states based on the value of an exclusive-OR of the bits in each partition.
- the next m check bits are set to logical states based on the values of an exclusive-OR of the ith bit (where i ranges from 1 to m) in each partition.
- the system is in the read (1) cycle.
- the stored information data bits are read from high speed memory 20 and through a data input latch 22, and the corresponding check bits are read from a check bit input latch 24; whereby they are caused to enter into an error corrector and detector (ECD) 26.
- ECD error corrector and detector
- the error corrector and detector 26 analyzes the data and, as the final step in the read(1) cycle, writes the corrected data to an ECD output latch 28.
- Three error status lines (which will be described more specifically in conjunction with FIGS. 2 and 6) are also made available to central processing unit (CPU) 30 at the completion of this cycle.
- Central processing unit (CPU) 30 and high speed memory 20 operatively interact with system 10 in a manner unique to the instant invention; however, apart from this interaction CPU 30 and memory 20 are conventional.
- X/Y decoder 12 is a standard two input decoder which enables one of four outputs based on the states of the two inputs.
- Check bit output latch 16, check bit input latch 24, data input latch 22, and ECD output latch 28 are all standard latches which prevent data movement except when enabled. They are used to synchronize data movement within the system during each of the four cycles.
- Data output buffer 32 and check bit output buffer 18 are standard buffers which cooperate in the provision of the synchronization functions of their associated latches, as well as restoring the signals to their proper voltage levels.
- This number of check bit positions is determined by the following calculation process.
- the number of rows in the H-Matrix of FIG. 1A is also equal to r (i.e., twelve (12) in the embodiment of FIG. 1A). It is to be appreciated that there is a predetermined relationship between the H-Matrix vertical column sequence of binary values of the r check bit positions and the vertical column sequence of binary values for the data bit positions in the respective ones of the n partitions of full data word length p. Specifically, in considering the sequence of twelve H-Matrix horizontally extending check positions C 0 , C 1 , . . .
- each of their columnar series of binary values has exactly one "binary one (1) value” from the corresponding row of the columnar series of binary values of any of the n partitions of the full data word of p bits.
- This enables logical one ("1") states to be generated in the corresponding bit position by exclusively-ORING the data bits which have a "1" in the same row as the check bit.
- the H-matrix data regeneration scheme of FIG. 1A results in generation of a single-error correction parity code which is characterized as both linear and self orthogonal.
- a parity matrix code produced using the H-Matrix of FIG. 1A would be called a "(44, 32, 4) single error correcting/burst error detecting (SEC/BED)" code.
- SEC/BED single error correcting/burst error detecting
- partition check bits and the burst check bits together serve as the error correction and as the multiple bit error code.
- partition check bits With respect to generation of partition check bits, the left edge of the matrix diagram of FIG. 3 is provided with the caption "Partition Check Bits", and the notations C 0 , C 1 . . . C n-1 inscribed therealong from the top to the bottom indicating that the partition check bits are a function of binary data items d 0 , d 1 , . . . d m-2 , d m-1 , d m . . .
- d mm-1 (i.e., the "check bit creating data" present in the H-matrix vertical column sequences of binary values respectively in the m bit positions in a respective different one of the n sequential partitions of each respective one of the r horizontally extending rows of bit positions beneath data bit positions d 0 . . . d 31 in the header of FIG. 1A) coded into the n sequential partitions of the p horizontally extending data bit positions of the H-matrix of FIG.
- each partition check bit is generated by a suitable logic network for exclusively-ORING the individual binary values constituting the "check bit creating data" within the data bit positions for a different individual partition of n partitions in r row of bit positions below the header of the H-matrix of FIG. 1A.
- each burst check bit is generated by a suitable logic network for exclusively-ORING the individual binary values constituting the check bit creating data in the corresponding individual sequential data bit position of each of the m sequential data positions in each of the n sequential partitions.
- a majority gate is also known as a "voter” because the output assumes the logic value of the majority of its three inputs.
- the H-matrix vertical column sequence of binary values in each data bit position (i.e., in each d 0 , d 1 , . . . d 31 ) has two binary ones ("1s").
- This provides two independent sources to regenerate a data word bit when performing error correction. For example, the following two logical equations are used to generate d 0 (i.e., final, or corrected value):
- the d 0 constituting the third independent voting source for the majority gate input is the d 0 as received from the memory.
- the three different versions of d 0 are fed to a majority logic function. If a single error occurs, only one of the three versions of d 0 may be erroneous, and the majority function logic will indicate the majority, namely the correct value by the uncorrupted two.
- a burst error consists of multiple errors in adjacent bits, for exampled errors in d 3 , d 4 , d 5 , d 6 and d 7 are a burst error of length 5, this type of error usually occurs in 5 bit byte organized memory systems in which one memory chip stores more than one bit at one addressable location. It is to be appreciated that the present invention can detect burst errors up to burst length 2 m-2. Any burst error with the burst length less than 2 m-2 will have at least 2 burst check bits affected by only one erroneous data bit (as will be subsequently amplified upon in a discussion of exclusively-ORING burst check bits). In accordance with well known parity code theory, a burst of burst length between 2 and 2 m-2 can be detected.
- the thusly generated code differs from the codes disclosed in the above referenced article "Orthogonal Latin Square Codes" by M. Y. Hsiao et al, by in that in certain important respects the code of the present invention is more universal.
- Latin square codes which are the subject of that article require p to be chosen from among a sequence of squared values of integers, i.e., 4, 16, 25, 36, 49 . . . etc.
- the present invention allows p to be other whole numbers.
- burst check bit C 8 is the parity check of data bits , d 0 , d 4 , d 8 , d 12 , d 16 , d 20 , d 24 , and d 28 ; and C 9 is the parity check of data bits d 1 , d 5 , d 9 , d 13 , d 17 , d 21 , d 25 , and d 29 ; and so on.
- the burst error detection is accomplished by exclusive-ORING the burst check bit character with the corresponding data bits from memory.
- the number of burst error parity checks (detectors) is p/n.
- the thusly generated check bits are effective to detect burst errors of burst lengths in the range 2 to 2 m-2.
- bit generator 14 may be provided is an application specific integrated circuit (ASIC) design engineered using a commercially available computed aided design computer program language.
- the computer program written in such a language is then used to implement production of the ASIC at a commercial facility having mask producing equipment that is responsive to the same language.
- VHSIC Very High Scale Integrated Circuit
- CAD computer aided design
- VHSIC Hardware Description Language VHSIC Hardware Description Language
- each of the n partitions of the p data bit positions of the H-Matrix is coded to have binary one ("1") values in each of n different H-matrix horizontal rows.
- the single error correction parity check bit for each partition, n is generated by exclusively-ORING (EORING) the bits of the corresponding partition.
- the burst error detection parity check bit is generated by exclusively-ORING (EORING) the binary value in the same position in each partition, n.
- FIG. 2 shows one embodiment of error corrector and detector (ECD) 26 and the distinct modules of which it is comprised.
- ECD error corrector and detector
- C/D error corrector/detector
- the error corrector/detector module also corrects the value of the first bit within that partition. Since there is one error corrector/detector for each partition, there are a total of n error corrector/detectors.
- the outputs of the Corrector/Detectors 41 and Correctors 42 are used to generate the corrected data output stream which is written to the ECD output latch 28 (FIG. 1).
- the error lines from the error corrector/detector modules 41 are used as inputs to an error status module 45, also within error corrector and detector 26.
- Error status module 45 provides no-error (NE), single bit error (SE), and multiple bit error (ME) status lines for connection to the central processing unit (CPU) 30 (FIG. 1).
- NE no-error
- SE single bit error
- ME multiple bit error
- check bit generator 14 provides single-error correction capability by way of one-step majority decoding having m data bits, with m as any whole number. Further among the advantages (as hereinabove stated) the code generated by check bit generator 14 lends itself to burst-error detection over predeterminable ranges of burst error lengths.
- FIG. 4 shows one embodiment of an error correction circuit 42 of error corrector module 26.
- the logic of the error correction circuit uses a one step majority (voting) decoding circuit 58 to determine the correct value for the bit in question.
- Each source may "vote” upon whether the correct value for the informational data bit is a logical "0" or "1".
- the final (corrected) value of the data bit is the value which receives either two or three "votes”.
- the three "votes" come from three sources of binary logic state signals. One of these sources is the informational data itself, arrow 52.
- Another of the three sources is the output, arrow 54, of an exclusive-0R (EOR) circuit 53 which as its inputs receives the partition check bit and the other "partition check bit creating data bits" of the corresponding partition of the H-matrix.
- the third of the three sources is the output, arrow 56, of an EOR circuit 57 which as its inputs receives the corresponding burst check bit and the other "burst check bit creating data bits" used to generate the burst check bit.
- FIG. 5 shows an embodiment of error corrector/detector (C/D) module 41. It performs the dual function of single bit error correction/burst error detection (SEC-BED).
- C/D error corrector/detector
- SEC-BED single bit error correction/burst error detection
- many of the components which are employed to implement error correction module 42 are shared in the implementation of C/D module 41. In the cases of such shared components, the same reference numeral as applied in FIG. 4 is applied in FIG. 5.
- Majority circuit 58 produces like corrected values in the same way they are produced in error correction module 42. That is to say, the corrected values are based upon the same three sources.
- EOR circuit 57 the output from exclusive-OR (EOR) circuit 57 is fed along a branch line 62 to be exclusively ORed with the input data bit (fed along a branch line 63) by an additional EOR circuit 61.
- the output, arrow 65, of EOR circuit 61 constitutes the error detection, or error output line.
- FIG. 6, is a description of one embodiment of the error status module 45 (FIG. 2) of the error corrector and detector (ECD) 26 (FIG. 2).
- the logic of the error status module uses the outputs of the error detectors in the error corrector/detector modules to generate the no-error (NE) status line signal 82, the single bit error (SE) status line signal 84, and the multi-bit error (ME) status line signal 86 for central processing unit (CPU) 30 (FIG. 1).
- the error status module uses suitable off-the-shelf logic components including 0R gates 88 (including one with inverted output 88'), AND gates 90, and inverter 91 in ways that can be readily interpreted by persons skilled in the art.
- An error correction and detection system which takes advantage of two independent check bit sources to provide robust error correction and detection.
- the system uses a unique data partitioning scheme which allows the detection of burst errors.
- the error correction and detection features of the system run in parallel providing the speed necessary for use in applications in which memory 20 is of a high speed type.
- the technique which the present invention employs for correcting an error and detecting errors separates into two different techniques enabling (i) correction of single error and (ii) burst error detection by one-step majority coding over significant ranges of data word size, p. All of the above advantages may be achieved with various memory word sizes by simply altering the number of error correction and detection modules.
- ASIC Application specific integrated circuit design and production processes (which have been discussed to some extent earlier herein in connection with check bit generator 14), can be employed to embody an entire system 10 in the form of massively integrated ASIC circuit devices, or even in the form of a single such circuit device.
- FIG. 7 illustrates one possible arrangement of partitioning of system 10 on a single integrated circuit (VLSI) chip 92.
- the component partitions of the chip 92 include: error corrector and detector (ECD) modules 94; error corrector (EC) modules 96; an error status circuit (ESC) 98; a check bits generator (CBG) 100; control logic (CL) 102; first and second subpartitions of input/output (I/O) logic 104a, 104b; peripheral buffers 106a, 106b; peripheral latches 108a, 108b, 108c; and bus structures 110a and 110b. Since every bit of a data word requires a correction circuit, the number of individual units of corrections logic incorporated into modules 94 and 96 is thirty-two (32) units. However, for purposes detecting burst error eight of these are designed to include error detecting capability.
- ECD modules 94 which occupy two (2) rows of chip area
- EC modules 96 which occupy six rows of chip area. This is shown in FIG. 7 by the relative areas of ECD modules 94 and EC modules 96.
Abstract
Description
M=AB+BC+AC (1)
d.sub.0 (i.e., one independent voting source)=C.sub.0 ⊕d.sub.1 ⊕d.sub.2 ⊕d.sub.3, (2)
d.sub.0 (i.e., another independent voting source)=C.sub.8 ⊕d.sub.4 ⊕d.sub.8 ⊕d.sub.12 ⊕D.sub.16 ⊕d.sub.20 ⊕d.sub.24 ⊕d.sub.28 (3)
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