US8527858B2 - Systems and methods for selective decode algorithm modification - Google Patents
Systems and methods for selective decode algorithm modification Download PDFInfo
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- US8527858B2 US8527858B2 US13/284,767 US201113284767A US8527858B2 US 8527858 B2 US8527858 B2 US 8527858B2 US 201113284767 A US201113284767 A US 201113284767A US 8527858 B2 US8527858 B2 US 8527858B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
- H03M13/3715—Adaptation to the number of estimated errors or to the channel state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6343—Error control coding in combination with techniques for partial response channels, e.g. recording
Definitions
- the present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data decoding.
- Various storage systems include data processing circuitry implemented with a data decoding circuit.
- a belief propagation based decoder circuit is used.
- an error floor is more severe because short cycles are unavoidable.
- Such short cycles make the messages in the belief propagation decoder correlate quickly and degrade the performance.
- a maximum likelihood decoder may be used as it does not exhibit the same limitations. However, such maximum likelihood decoders are typically too complex for practical implementation.
- Various embodiments of the present invention provide data processing systems. Such systems include a combination data decoder circuit.
- the combination data decoder circuit includes a first decoder circuit and a second decoder circuit.
- the first decoder circuit is operable to apply a first data decode algorithm to a decoder input to yield a decoded output.
- the second decoder circuit is operable to apply a second data decode algorithm to a subset of the decoded output to modify at least one element of the decoded output to yield a modified decoded output.
- the data processing system further includes a data detector circuit that is operable to apply a data detection algorithm to a data set to yield a detected output. In such cases, the decoder input is derived from the detected output.
- the data detection algorithm may be, but is not limited to, a maximum a posteriori data detection algorithm or a Viterbi detection algorithm.
- the data processing system is implemented as part of a storage device or a receiving device. In one or more cases, the data processing system is implemented as part of an integrated circuit.
- the decoded output is a first decoded output.
- the first decoder output is operable to apply the first data decode algorithm to the decoder input guided by the modified decoded output to yield a second decoded output.
- the first data decode algorithm is a belief propagation data decode algorithm
- the second data decode algorithm is a maximum likelihood data decode algorithm.
- the combination data decoder circuit further includes a controller circuit operable to selectively control generation of the modified decoded output.
- the controller circuit enables generation of the modified decoded output when: a number of iterations of the first decoder circuit applying the first data decode algorithm to a decoder input is greater than a first threshold value; a number of unsatisfied checks corresponding to the decoded output is less than a second threshold value; and the unsatisfied checks corresponding to the decoded output is the same as the unsatisfied checks corresponding to a previous decoded output.
- the first threshold value is three
- the second threshold value is ten.
- the methods include: applying a first data decode algorithm to a decoder input to yield a first decoded output; applying a second data decode algorithm to a subset of the first decoded output to modify at least one element of the decoded output to yield a modified decoded output; and applying the first data decode algorithm to the decoder input guided by the modified decoded output to yield a second decoded output.
- the methods further include applying a data detection algorithm to a data set to yield a detected output, wherein the decoder input is derived from the detected output.
- the methods further include: receiving an analog input; converting the analog input to a series of digital samples; and equalizing the series of digital samples to yield the data set.
- the data detection algorithm may be, but is not limited to, a maximum a posteriori data detection algorithm or a Viterbi detection algorithm.
- the first data decode algorithm is a belief propagation data decode algorithm
- the second data decode algorithm is a maximum likelihood data decode algorithm.
- the methods further include determining that there are at least one failed checksum associated with the first decoded output. In such instances, the subset of the first decoded output includes elements of the first decoded output that correspond to the at least one failed checksum. In some cases, the methods further include determining that the same at least one failed checksum occurs for at least two consecutive applications of the first data decode algorithm to the decoder input.
- FIG. 1 b depicts a controller circuit that may be used in relation to the combination decoder circuit of FIG. 1 in accordance with various embodiments of the present invention
- FIG. 2 is a flow diagram showing method for selectively combined data decoding in accordance with various embodiments of the present invention
- FIG. 3 shows a storage device including combination data decoder circuitry in accordance with one or more embodiments of the present invention.
- Various embodiments of the present invention provide data processing systems that include a data decoder circuit that includes a low complexity decoder circuit and a partial maximum likelihood parity check decoder circuit that is selectively used to modify an output of the low complexity decoder circuit when a possible trapping set is detected.
- the aforementioned approach allows for using data decoder circuits that exhibit relatively low complexity such as, for example, a belief propagation decoder circuit, while using another decoder algorithm to correct errors that are not correctable by the low complexity decoder algorithm.
- the complexity of the combination of the partial maximum likelihood parity check decoder circuit and the belief propagation decoder circuit is substantially less than that of a maximum likelihood decoder circuit.
- a data processing circuit 100 that includes a combination data decoder circuit 170 including a combination of a low complexity decoder circuit 166 and a partial maximum likelihood decoder circuit 168 in accordance with one or more embodiments of the present invention.
- Data processing circuit 100 includes an analog front end circuit 110 that receives an analog signal 105 .
- Analog front end circuit 110 processes analog signal 105 and provides a processed analog signal 112 to an analog to digital converter circuit 114 .
- Analog front end circuit 110 may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit 110 .
- analog signal 105 is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). In other cases, analog signal 105 is derived from a receiver circuit (not shown) that is operable to receive a signal from a transmission medium (not shown).
- the transmission medium may be wired or wireless.
- Analog to digital converter circuit 114 converts processed analog signal 112 into a corresponding series of digital samples 116 .
- Analog to digital converter circuit 114 may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention.
- Digital samples 116 are provided to an equalizer circuit 120 .
- Equalizer circuit 120 applies an equalization algorithm to digital samples 116 to yield an equalized output 125 .
- equalizer circuit 120 is a digital finite impulse response filter circuit as are known in the art.
- equalizer 120 includes sufficient memory to maintain one or more codewords until a data detector circuit 130 is available for processing, and for multiple processes through data detector circuit 130 .
- maximum a posteriori data detection algorithm or “maximum a posteriori data detector circuit” are used in their broadest sense to mean any maximum a posteriori detection algorithm or detector circuit or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm, or corresponding detector circuits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present invention. Data detector circuit 130 is started based upon availability of a data set from equalizer circuit 120 or from a central memory circuit 150 .
- Detector output 196 includes soft data.
- soft data is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a corresponding bit position or group of bit positions has been correctly detected.
- the soft data or reliability data is log likelihood ratio data as is known in the art.
- Detected output 196 is provided to a local interleaver circuit 142 .
- Local interleaver circuit 142 is operable to shuffle sub-portions (i.e., local chunks) of the data set included as detected output and provides an interleaved codeword 146 that is stored to central memory circuit 150 .
- Interleaver circuit 142 may be any circuit known in the art that is capable of shuffling data sets to yield a re-arranged data set.
- Interleaved codeword 146 is stored to central memory circuit 150 .
- Interleaved codeword 146 is comprised of a number of encoded sub-codewords designed to reduce the complexity of a downstream data decoder circuit while maintaining reasonable processing ability.
- Controller circuit 175 utilizes decoder output 167 and checksum indices 169 to determine if a potential trapping set condition has occurred. Where a potential trapping set condition has occurred, an LLR subset output 177 (a portion of decoder output 167 ) and corresponding index outputs 176 (i.e., a portion of checksum indices 169 corresponding to LLR subset output 177 ) are provided by controller circuit 175 to partial maximum likelihood decoder circuit 168 . Partial maximum likelihood decoder circuit 168 applies a maximum likelihood decoder algorithm to LLR subset output 177 in an effort to correct any remaining unsatisfied checks.
- the complexity of partial maximum likelihood decoder circuit 168 is substantially less than the complexity of implementing a corresponding maximum likelihood decoder circuit capable of handing an entire codeword.
- the corresponding elements of LLR subset output 177 are modified to corrected values 179 that are fed back to low complexity decoder circuit 166 where they are used in place of the corresponding element of decoder output 167 to guide subsequent application of the decoder algorithm to decoder input 152 .
- partial maximum likelihood decoder circuit 168 is implemented using the maximum likelihood decoder approach disclosed in Viterbi, Andrew J., “ERROR BOUNDS FOR CONVOLUTION CODES AND AN ASYMPTITICALLY OPTIMUM DECODING ALGORITHM”, IEEE Transactions on Information Theory, Vol. IT-13, No. 2, April 1967. The entirety of the aforementioned reference is incorporated herein by reference for all purposes. Where a potential trapping set condition has not been identified and one or more additional local iterations remain, low complexity decoder circuit 166 is triggered to re-apply the decoder algorithm to decoder input 152 guided by decoder output 167 .
- a potential trapping set condition is considered to have occurred where the number of remaining unsatisfied checks after application of the decoder algorithm to decoder input 152 is less than ten, and the indexes corresponding to the remaining unsatisfied checks have not changed for at least two local iterations (i.e., passes through low complexity decoder circuit 166 ).
- controller circuit 175 is not enabled to indicate a potential trapping set condition until at least four local iterations of decoder algorithm to decoder input 152 have completed. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other indicia that may be used to define the occurrence of a potential trapping set condition and/or to trigger operation of partial maximum likelihood decoder circuit 168 .
- controller circuit 175 determines whether the data decoding algorithm converged. Where the data decoding algorithm failed to converge and no more local iterations (iterations through low complexity decoder circuit 166 ), controller circuit 175 provides a decoder output 154 (i.e., decoder output 167 ) back to central memory circuit 150 via global interleaver/de-interleaver circuit 184 . Prior to storage of decoded output 154 to central memory circuit 150 , decoded output 154 is globally de-interleaved to yield a globally de-interleaved output 188 that is stored to central memory circuit 150 .
- decoder output 154 Prior to storage of decoded output 154 to central memory circuit 150 , decoded output 154 is globally de-interleaved to yield a globally de-interleaved output 188 that is stored to central memory circuit 150 .
- the global de-interleaving reverses the global interleaving earlier applied to stored codeword 186 to yield decoder input 152 .
- a previously stored de-interleaved output 188 is accessed from central memory circuit 150 and locally de-interleaved by a de-interleaver circuit 144 .
- De-interleaver circuit 144 re-arranges decoder output 148 to reverse the shuffling originally performed by interleaver circuit 142 .
- a resulting de-interleaved output 197 is provided to data detector circuit 130 where it is used to guide subsequent detection of a corresponding data set receive as equalized output 125 .
- controller circuit 175 provides an output codeword 172 to a de-interleaver circuit 180 .
- De-interleaver circuit 180 rearranges the data to reverse both the global and local interleaving applied to the data to yield a de-interleaved output 182 .
- De-interleaved output 182 is provided to a hard decision output circuit 190 .
- Hard decision output circuit 190 is operable to re-order data sets that may complete out of order back into their original order. The originally ordered data sets are then provided as a hard decision output 192 .
- controller circuit 175 An example of operation of controller circuit 175 is provided in the following pseudo-code:
- Controller circuit 101 includes an LLR subset register 102 that stores each element of decoder output 167 that corresponds to a non-zero value of a checksum identified as one of checksum indices 169 .
- An LLR subset register output 103 is provided by LLR subset register 102 .
- controller circuit 101 includes an unsatisfied check index register 106 that stores each index for which one or more instances of decoder output 167 stored to LLR subset register 102 .
- Controller circuit 101 also includes a codeword completion circuit 113 that counts decoder outputs 167 to determine whether all instances of a codeword have been received. Where a completed codeword is received, a codeword complete output 117 is asserted high.
- a local iteration counter circuit 118 receives codeword complete output 117 and counts the number of local iterations that have been applied to the particular codeword (received as decoder output 167 ). The number of local iterations is provided as a local iteration count value 119 .
- a count output greater than N circuit receives local iteration count value 119 and asserts a count value greater than N output 126 whenever local iteration count value 119 is greater than N. In some cases, N is three. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of N that may be used in relation to different embodiments of the present invention.
- a count output equals maximum local iterations circuit 121 receives local iteration count value 119 and asserts a count value equals maximum local iterations output 122 whenever local iteration count value 119 equals the defined maximum number of local iterations. is greater than N. In some cases, N is three. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of N that may be used in relation to different embodiments of the present invention.
- M count output 132 indicates that the number of unsatisfied checks is not zero and count value equals maximum local iterations output 122 indicates the maximum number of local iterations have been performed
- a decoded output generator circuit 123 provides a derivative of decoder output 167 as decoded output 154 .
- LLR subset output generator circuit 104 provides LLR subset register output 103 as LLR subset output 177 whenever same indexes output 112 is asserted, count value greater than N output 126 is asserted, and M count output 132 are all asserted.
- a data decoder circuit is available (block 240 ). Where the data decoder circuit is available (block 240 ), a previously stored derivative of a detected output is accessed from the central memory (block 245 ). A low complexity data decode algorithm is applied to the derivative of the detected output to yield a decoded output (block 250 ).
- the low complexity decode algorithm maybe be any data decode algorithm known in the art that is less complex to implement than a maximum likelihood decoder algorithm.
- the low complexity data decode algorithm is a belief propagation data decode algorithm as are known in the art. Such a belief propagation data decode algorithm may be implemented similar to that discussed in Pearl, Judea, “REVEREND BAYES ON INFERENCE ENGINES: A DISTRIBUTED HIERARCHAL APPROACH”, AAAI-82 Proceedings, 1982.
- N is four. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of N that may be used in relation to different embodiments of the present invention. Where the number of local iterations has not exceeded the threshold value N (block 265 ), the processes of blocks 250 - 265 are repeated for the same data set using the previous decoded output as a guide.
- a partial maximum likelihood data decode algorithm is applied to a subset of the decoded output corresponding to the remaining unsatisfied checks to yield a partial maximum likelihood soft data output (block 285 ).
- the complexity of the complexity of the partial maximum likelihood data decode algorithm is substantially less than the complexity of a corresponding maximum likelihood decoder circuit capable of handing an entire codeword.
- the partial maximum likelihood data decode algorithm is implemented using the maximum likelihood decoder approach disclosed in Viterbi, Andrew J., “ERROR BOUNDS FOR CONVOLUTION CODES AND AN ASYMPTITICALLY OPTIMUM DECODING ALGORITHM”, IEEE Transactions on Information Theory, Vol. IT-13, No. 2, April 1967.
- the soft data of the decoded output is forced to be equal to the corresponding partial maximum likelihood soft data to yield a modified decoded output (block 290 ), and the processes of blocks 250 - 290 are repeated for the same data set using the modified decoded output as a guide.
- read/write head assembly 376 is accurately positioned by motor controller 368 over a desired data track on disk platter 378 .
- Motor controller 368 both positions read/write head assembly 376 in relation to disk platter 378 and drives spindle motor 372 by moving read/write head assembly to the proper data track on disk platter 378 under the direction of hard disk controller 366 .
- Spindle motor 372 spins disk platter 378 at a determined spin rate (RPMs).
- the sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter 378 .
- This minute analog signal is transferred from read/write head assembly 376 to read channel circuit 310 via preamplifier 370 .
- Preamplifier 370 is operable to amplify the minute analog signals accessed from disk platter 378 .
- read channel circuit 310 decodes and digitizes the received analog signal to recreate the information originally written to disk platter 378 .
- This data is provided as read data 303 to a receiving circuit.
- a write operation is substantially the opposite of the preceding read operation with write data 301 being provided to read channel circuit 310 . This data is then encoded and written to disk platter 378 .
- data decoding applied to the information received from disk platter 378 may not converge.
- a second data decoder and/or decoding algorithm may be applied to a localized portion of the information to correct one or more errors associated with the possible trapping set or other impediment to convergence.
- Such multi-level decoding may be performed using a data decoder circuit similar to that discussed above in relation to FIGS. 1 a - 1 b , and/or may be done using a process similar to that discussed above in relation to FIG. 2 .
- storage system may utilize SATA, SAS or other storage technologies known in the art.
- storage system 300 may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system.
- RAID redundant array of inexpensive disks or redundant array of independent disks
- various functions or blocks of storage system 400 may be implemented in either software or firmware, while other functions or blocks are implemented in hardware.
- Data transmission system 400 includes a transmitter 410 that is operable to transmit encoded information via a transfer medium 430 as is known in the art.
- the encoded data is received from transfer medium 430 by receiver 420 .
- Transceiver 420 incorporates combination data decoder circuitry. While processing received data, received data is converted from an analog signal to a series of corresponding digital samples, and the digital samples are equalized to yield an equalized output. The equalized output is then provided to a data processing circuit including both a data detector circuit and a data decoder circuit.
- transfer medium 430 may be any transfer medium known in the art including, but not limited to, a wireless medium, an optical medium, or a wired medium. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of transfer mediums that may be used in relation to different embodiments of the present invention.
- Such integrated circuits may include all of the functions of a given block, system or circuit, or only a subset of the block, system or circuit. Further, elements of the blocks, systems or circuits may be implemented across multiple integrated circuits. Such integrated circuits may be any type of integrated circuit known in the art including, but are not limited to, a monolithic integrated circuit, a flip chip integrated circuit, a multichip module integrated circuit, and/or a mixed signal integrated circuit. It should also be noted that various functions of the blocks, systems or circuits discussed herein may be implemented in either software or firmware. In some such cases, the entire system, block or circuit may be implemented using its software or firmware equivalent. In other cases, the one part of a given system, block or circuit may be implemented in software or firmware, while other parts are implemented in hardware.
Abstract
Description
where b represents a bit of decoded
where li is the soft data (i.e., LLR data) associated with bi. Accordingly, the probability for a given hard decision value bi may be approximated by the following equation:
If (number of unsatisfied checks == 0) |
{ |
provide |
} |
Else if (number of unsatisfied checks > 0 && number of local |
iterations == maximum) |
{ |
provide |
} |
Else if (number of unsatisfied checks > 0 && |
[number of unsatisfied checks >= M OR |
number of local iterations is < N OR |
|
{ |
provide |
circuit 166 |
} |
Else if (number of unsatisfied checks > 0 && |
[number of unsatisfied checks < M AND |
number of local iterations is >= N OR |
|
{ |
provide |
circuit 168 |
} |
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US9324371B2 (en) * | 2012-07-02 | 2016-04-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Systems and methods for multi-stage decoding processing |
US10164657B2 (en) | 2014-04-03 | 2018-12-25 | Seagate Technology Llc | Systems and methods for differential message scaling in a decoding process |
Families Citing this family (3)
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US9886342B2 (en) | 2015-10-28 | 2018-02-06 | Sandisk Technologies Llc | Storage device operations based on bit error rate (BER) estimate |
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Citations (124)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0522578A2 (en) | 1991-07-12 | 1993-01-13 | Pioneer Electronic Corporation | Noise removing circuit |
US5278846A (en) | 1990-06-11 | 1994-01-11 | Matsushita Electric Industrial Co., Ltd. | Digital signal decoder |
US5278703A (en) | 1991-06-21 | 1994-01-11 | Digital Equipment Corp. | Embedded servo banded format for magnetic disks for use with a data processing system |
US5325402A (en) | 1991-04-30 | 1994-06-28 | Nec Corporation | Method and arrangement for estimating data sequences transmsitted using Viterbi algorithm |
US5392299A (en) | 1992-01-15 | 1995-02-21 | E-Systems, Inc. | Triple orthogonally interleaed error correction system |
EP0631277A3 (en) | 1993-06-22 | 1995-02-22 | Quantum Corp | ID-less data sector format and data controller for disk drive. |
US5471500A (en) | 1994-03-08 | 1995-11-28 | At&T Ipm Corp. | Soft symbol decoding |
US5513192A (en) | 1992-08-28 | 1996-04-30 | Sun Microsystems, Inc. | Fault tolerant disk drive system with error detection and correction |
US5523903A (en) | 1993-12-23 | 1996-06-04 | International Business Machines Corporation | Sector architecture for fixed block disk drive |
US5550870A (en) | 1994-03-02 | 1996-08-27 | Lucent Technologies Inc. | Viterbi processor |
US5612964A (en) | 1991-04-08 | 1997-03-18 | Haraszti; Tegze P. | High performance, fault tolerant orthogonal shuffle memory and method |
US5701314A (en) | 1995-12-21 | 1997-12-23 | Cirrus Logic, Inc. | On-the-fly error correction using thermal asperity erasure pointers from a sampled amplitude read channel in a magnetic disk drive |
US5710784A (en) | 1993-09-24 | 1998-01-20 | Qualcomm Incorporated | Multirate serial viterbi decoder for code division multiple access system applications |
US5712861A (en) | 1994-07-12 | 1998-01-27 | Mitsubishi Denki Kabushiki Kaisha | Error correcting method and decoder with improved reliability |
US5717706A (en) | 1994-03-04 | 1998-02-10 | Sony Corporation | Apparatus and method for detecting signal points using signal point-mapping |
US5802118A (en) | 1996-07-29 | 1998-09-01 | Cirrus Logic, Inc. | Sub-sampled discrete time read channel for computer storage systems |
US5844945A (en) | 1994-04-12 | 1998-12-01 | Goldstar Co., Ltd. | Viterbi decoder for a high definition television |
US5898710A (en) | 1995-06-06 | 1999-04-27 | Globespan Technologies, Inc. | Implied interleaving, a family of systematic interleavers and deinterleavers |
US5923713A (en) | 1996-02-28 | 1999-07-13 | Sony Corporation | Viterbi decoder |
US5978414A (en) | 1996-07-03 | 1999-11-02 | Matsushita Electric Industrial Co., Ltd. | Transmission rate judging unit |
US5983383A (en) | 1997-01-17 | 1999-11-09 | Qualcom Incorporated | Method and apparatus for transmitting and receiving concatenated code data |
US6005897A (en) | 1997-12-16 | 1999-12-21 | Mccallister; Ronald D. | Data communication system and method therefor |
US6023783A (en) | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
US6029264A (en) | 1997-04-28 | 2000-02-22 | The Trustees Of Princeton University | System and method for error correcting a received data stream in a concatenated system |
US6065149A (en) | 1996-11-21 | 2000-05-16 | Matsushita Electric Industrial Co., Ltd. | Error correction device for a communication system |
US6145110A (en) | 1998-06-22 | 2000-11-07 | Ericsson Inc. | Digital data decoder that derives codeword estimates from soft data |
US6216249B1 (en) | 1999-03-03 | 2001-04-10 | Cirrus Logic, Inc. | Simplified branch metric for reducing the cost of a trellis sequence detector in a sampled amplitude read channel |
US6216251B1 (en) | 1999-04-30 | 2001-04-10 | Motorola Inc | On-chip error detection and correction system for an embedded non-volatile memory array and method of operation |
US6229467B1 (en) | 1999-05-28 | 2001-05-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Correction static errors in a/d-converter |
US6266795B1 (en) | 1999-05-28 | 2001-07-24 | Lucent Technologies Inc. | Turbo code termination |
US6317472B1 (en) | 1997-08-07 | 2001-11-13 | Samsung Electronics Co., Ltd. | Viterbi decoder |
US6351832B1 (en) | 1999-05-28 | 2002-02-26 | Lucent Technologies Inc. | Turbo code symbol interleaver |
US6366624B1 (en) * | 1998-11-30 | 2002-04-02 | Ericsson Inc. | Systems and methods for receiving a modulated signal containing encoded and unencoded bits using multi-pass demodulation |
US6377610B1 (en) | 1997-04-25 | 2002-04-23 | Deutsche Telekom Ag | Decoding method and decoding device for a CDMA transmission system for demodulating a received signal available in serial code concatenation |
US6381726B1 (en) | 1999-01-04 | 2002-04-30 | Maxtor Corporation | Architecture for soft decision decoding of linear block error correcting codes |
US6438717B1 (en) | 1999-05-26 | 2002-08-20 | 3Com Corporation | High speed parallel bit error rate tester |
US6473878B1 (en) | 1999-05-28 | 2002-10-29 | Lucent Technologies Inc. | Serial-concatenated turbo codes |
US6476989B1 (en) | 1996-07-09 | 2002-11-05 | International Business Machines Corporation | Radial self-propagation pattern generation for disk file servowriting |
US20030063405A1 (en) | 2001-10-02 | 2003-04-03 | Ming Jin | Method and apparatus for detecting media defects |
US20030081693A1 (en) | 2001-07-11 | 2003-05-01 | Raghavan Sreen A. | Low complexity high-speed communications transceiver |
US20030087634A1 (en) | 2001-07-11 | 2003-05-08 | Raghavan Sreen A. | 10165368High-speed multi-channel communications transceiver with inter-channel interference filter |
US20030112896A1 (en) | 2001-07-11 | 2003-06-19 | Raghavan Sreen A. | Multi-channel communications transceiver |
US6625775B1 (en) | 1998-12-10 | 2003-09-23 | Samsung Electronics Co., Ltd. | Encoder/decoder with serial concatenated structure in communication system |
US6657803B1 (en) | 1999-11-22 | 2003-12-02 | Seagate Technology Llc | Method and apparatus for data error recovery using defect threshold detector and viterbi gain |
US6671404B1 (en) | 1997-02-14 | 2003-12-30 | Hewlett-Packard Development Company, L.P. | Method and apparatus for recognizing patterns |
US20040071206A1 (en) | 2002-08-13 | 2004-04-15 | Fujitsu Limited. | Digital filter adaptively learning filter coefficient |
US20040098659A1 (en) | 2002-11-18 | 2004-05-20 | Bjerke Bjorn A. | Rate-compatible LDPC codes |
US6748034B2 (en) | 1997-12-19 | 2004-06-08 | Sony Corporation | Viterbi decoding apparatus and viterbi decoding method |
US6757862B1 (en) | 2000-08-21 | 2004-06-29 | Handspring, Inc. | Method and apparatus for digital data error correction coding |
US6785863B2 (en) | 2002-09-18 | 2004-08-31 | Motorola, Inc. | Method and apparatus for generating parity-check bits from a symbol set |
US6788654B1 (en) | 1998-01-29 | 2004-09-07 | Nippon Hoso Kyokai | Digital data receiver |
US6810502B2 (en) | 2000-01-28 | 2004-10-26 | Conexant Systems, Inc. | Iteractive decoder employing multiple external code error checks to lower the error floor |
US20050010855A1 (en) | 2003-07-09 | 2005-01-13 | Itay Lusky | Reduced complexity decoding for trellis coded modulation |
US20050078399A1 (en) | 2003-10-10 | 2005-04-14 | Seagate Technology Llc | Using data compression to achieve lower linear bit densities on a storage medium |
US20050111540A1 (en) | 2001-11-21 | 2005-05-26 | David Modrie | Adaptive equalizer operating at a sampling rate asynchronous to the data rate |
US20050157780A1 (en) | 2003-12-17 | 2005-07-21 | Werner Carl W. | Signaling system with selectively-inhibited adaptive equalization |
US20050195749A1 (en) | 2004-03-05 | 2005-09-08 | Elmasry George F. | Method and system for capacity analysis for On The Move adhoc wireless packet-switched networks |
US20050216819A1 (en) | 2004-02-19 | 2005-09-29 | Trellisware Technologies, Inc. | Method and apparatus for communications using turbo like codes |
US20050273688A1 (en) | 2004-06-02 | 2005-12-08 | Cenk Argon | Data communication system with multi-dimensional error-correction product codes |
US6980382B2 (en) | 2001-11-09 | 2005-12-27 | Fujitsu Limited | Magnetic disk drive system |
US6986098B2 (en) | 2001-11-20 | 2006-01-10 | Lsi Logic Corporation | Method of reducing miscorrections in a post-processor using column parity checks |
US20060020872A1 (en) | 2004-07-21 | 2006-01-26 | Tom Richardson | LDPC encoding methods and apparatus |
US20060031737A1 (en) | 2004-02-19 | 2006-02-09 | Trellisware Technologies, Inc. | Method and apparatus for communications using improved turbo like codes |
US7010051B2 (en) | 2000-03-24 | 2006-03-07 | Sony Corporation | Coding apparatus, coding method and recording medium having coded program recorded therein, and decoding apparatus, decoding method and recording medium having decoded program recorded therein |
US7047474B2 (en) | 2002-12-23 | 2006-05-16 | Do-Jun Rhee | Decoding concatenated codes via parity bit recycling |
US7058873B2 (en) | 2002-11-07 | 2006-06-06 | Carnegie Mellon University | Encoding method using a low density parity check code with a column weight of two |
US20060123285A1 (en) | 2004-11-16 | 2006-06-08 | De Araujo Daniel F | Dynamic threshold scaling in a communication system |
US20060140311A1 (en) | 2004-12-23 | 2006-06-29 | Agere Systems Inc. | Composite data detector and a method for detecting data |
US7073118B2 (en) | 2001-09-17 | 2006-07-04 | Digeo, Inc. | Apparatus and method for saturating decoder values |
US20060168493A1 (en) | 2005-01-24 | 2006-07-27 | Agere Systems Inc. | Data detection and decoding system and method |
US7093179B2 (en) | 2001-03-22 | 2006-08-15 | University Of Florida | Method and coding means for error-correction utilizing concatenated parity and turbo codes |
US20060195772A1 (en) | 2005-02-28 | 2006-08-31 | Nils Graef | Method and apparatus for evaluating performance of a read channel |
US20060210002A1 (en) | 2005-03-03 | 2006-09-21 | Xueshi Yang | Timing recovery in a parallel channel communication system |
US7113356B1 (en) | 2002-09-10 | 2006-09-26 | Marvell International Ltd. | Method for checking the quality of servo gray codes |
US20060248435A1 (en) | 2005-04-29 | 2006-11-02 | Haratsch Erich F | Method and apparatus for iterative error-erasure decoding |
US7136244B1 (en) | 2002-02-22 | 2006-11-14 | Western Digital Technologies, Inc. | Disk drive employing data averaging techniques during retry operations to facilitate data recovery |
US20060256670A1 (en) | 2005-05-16 | 2006-11-16 | Samsung Electronics Co., Ltd. | Signal-to-noise ratio measurement apparatus and method for signal read out of optical disc |
US20070011569A1 (en) | 2005-06-20 | 2007-01-11 | The Regents Of The University Of California | Variable-rate low-density parity check codes with constant blocklength |
US7173783B1 (en) | 2001-09-21 | 2007-02-06 | Maxtor Corporation | Media noise optimized detector for magnetic recording |
US7184486B1 (en) | 2000-04-27 | 2007-02-27 | Marvell International Ltd. | LDPC encoder and decoder and method thereof |
US20070047121A1 (en) | 2005-08-26 | 2007-03-01 | Eleftheriou Evangelos S | Read channel apparatus for asynchronous sampling and synchronous equalization |
US20070047635A1 (en) | 2005-08-24 | 2007-03-01 | Stojanovic Vladimir M | Signaling system with data correlation detection |
US7191378B2 (en) | 2002-07-03 | 2007-03-13 | The Directv Group, Inc. | Method and system for providing low density parity check (LDPC) encoding |
US7203015B2 (en) | 2003-07-31 | 2007-04-10 | Kabushiki Kaisha Toshiba | Method and apparatus for decoding sync marks in a disk |
US20070110200A1 (en) | 2005-11-15 | 2007-05-17 | Gokhan Mergen | Equalizer for a receiver in a wireless communication system |
US7257764B2 (en) | 2003-11-03 | 2007-08-14 | Broadcom Corporation | FEC (Forward Error Correction) decoder with dynamic parameters |
US20070230407A1 (en) | 2006-03-31 | 2007-10-04 | Petrie Michael C | Dynamic, adaptive power control for a half-duplex wireless communication system |
US20070286270A1 (en) | 2001-09-05 | 2007-12-13 | Mediatek Inc. | Read channel apparatus and method for an optical storage system |
US7313750B1 (en) | 2003-08-06 | 2007-12-25 | Ralink Technology, Inc. | Efficient soft decision demapper to minimize viterbi decoder complexity |
US20080049825A1 (en) | 2006-08-25 | 2008-02-28 | Broadcom Corporation | Equalizer with reorder |
US20080055122A1 (en) | 2006-07-31 | 2008-03-06 | Agere Systems Inc. | Systems and Methods for Code Based Error Reduction |
US20080065970A1 (en) | 2006-07-31 | 2008-03-13 | Agere Systems Inc. | Systems and Methods for Code Dependency Reduction |
US20080069373A1 (en) | 2006-09-20 | 2008-03-20 | Broadcom Corporation | Low frequency noise reduction circuit architecture for communications applications |
US7370258B2 (en) | 2005-04-28 | 2008-05-06 | Sandbridge Technologies Inc. | Iterative concatenated convolutional Reed-Solomon decoding method |
US20080168330A1 (en) | 2007-01-08 | 2008-07-10 | Agere Systems Inc. | Systems and methods for prioritizing error correction data |
US7430256B2 (en) | 2003-09-26 | 2008-09-30 | Samsung Electronics Co., Ltd. | Method and apparatus for providing channel state information |
US20080276156A1 (en) | 2007-05-01 | 2008-11-06 | Texas A&M University System | Low density parity check decoder for regular ldpc codes |
EP1814108B1 (en) | 2005-09-12 | 2008-11-26 | Sony Corporation | Noise reducing apparatus, method and program and sound pickup apparatus for electronic equipment |
US7502189B2 (en) | 2000-10-23 | 2009-03-10 | Hitachi Global Storage Technologies Japan, Ltd. | Apparatus, signal-processing circuit and device for magnetic recording system |
US7505537B1 (en) | 2003-03-25 | 2009-03-17 | Marvell International Ltd. | System and method for controlling gain and timing phase in a presence of a first least mean square filter using a second adaptive filter |
US7509927B2 (en) | 2006-01-25 | 2009-03-31 | Comfort-Sinusverteiler Gmbh | Hydraulic header for a heating system |
US7523375B2 (en) | 2005-09-21 | 2009-04-21 | Distribution Control Systems | Set of irregular LDPC codes with random structure and low encoding complexity |
US20090185643A1 (en) | 2008-01-22 | 2009-07-23 | Fitzpatrick Kelly K | Methods and Apparatus for Map Detection with Reduced Complexity |
US20090199071A1 (en) | 2008-02-05 | 2009-08-06 | Agere Systems Inc. | Systems and Methods for Low Cost LDPC Decoding |
US20090235146A1 (en) | 2008-03-17 | 2009-09-17 | Agere Systems Inc. | Systems and Methods for Using Intrinsic Data for Regenerating Data from a Defective Medium |
US20090235116A1 (en) | 2008-03-17 | 2009-09-17 | Agere Systems Inc. | Systems and Methods for Regenerating Data from a Defective Medium |
US20090259915A1 (en) | 2004-10-12 | 2009-10-15 | Michael Livshitz | Structured low-density parity-check (ldpc) code |
US20090274247A1 (en) | 2008-04-30 | 2009-11-05 | Richard Leo Galbraith | Detection of synchronization mark from output of matched filter upstream of viterbi detector |
US20090273492A1 (en) | 2008-05-02 | 2009-11-05 | Lsi Corporation | Systems and Methods for Queue Based Data Detection and Decoding |
US20100042890A1 (en) | 2008-08-15 | 2010-02-18 | Lsi Corporation | Error-floor mitigation of ldpc codes using targeted bit adjustments |
US20100042877A1 (en) | 2007-10-01 | 2010-02-18 | Weijun Tan | Systems and Methods for Media Defect Detection |
US20100050043A1 (en) | 2006-12-01 | 2010-02-25 | Commissariat A L'energie Atomique | Method and device for decoding ldpc codes and communication apparatus including such device |
US20100061492A1 (en) | 2008-09-05 | 2010-03-11 | Lsi Corporation | Reduced Frequency Data Processing Using a Matched Filter Set Front End |
US20100070837A1 (en) | 2008-09-17 | 2010-03-18 | LSI Corporatrion | Power Reduced Queue Based Data Detection and Decoding Systems and Methods for Using Such |
US7702989B2 (en) | 2006-09-27 | 2010-04-20 | Agere Systems Inc. | Systems and methods for generating erasure flags |
US7712008B2 (en) | 2006-01-26 | 2010-05-04 | Agere Systems Inc. | Systems and methods for error reduction associated with information transfer |
US7738201B2 (en) | 2006-08-18 | 2010-06-15 | Seagate Technology Llc | Read error recovery using soft information |
US20100164764A1 (en) | 2008-05-19 | 2010-07-01 | Ratnakar Aravind Nayak | Systems and Methods for Mitigating Latency in a Data Detector Feedback Loop |
US7752523B1 (en) | 2006-02-13 | 2010-07-06 | Marvell International Ltd. | Reduced-complexity decoding of parity check codes |
US20100185914A1 (en) | 2007-09-28 | 2010-07-22 | Weijun Tan | Systems and Methods for Reduced Complexity Data Processing |
WO2010101578A1 (en) | 2009-03-05 | 2010-09-10 | Lsi Corporation | Improved turbo-equalization methods for iterative decoders |
US20110075569A1 (en) | 2008-04-18 | 2011-03-31 | Link_A_Media Devices Corporation | Obtaining parameters for minimizing an error event probability |
US20110080211A1 (en) | 2008-11-20 | 2011-04-07 | Shaohua Yang | Systems and Methods for Noise Reduced Data Detection |
US20110167246A1 (en) | 2010-01-04 | 2011-07-07 | Lsi Corporation | Systems and Methods for Data Detection Including Dynamic Scaling |
-
2011
- 2011-10-28 US US13/284,767 patent/US8527858B2/en active Active
Patent Citations (138)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5278846A (en) | 1990-06-11 | 1994-01-11 | Matsushita Electric Industrial Co., Ltd. | Digital signal decoder |
US5612964A (en) | 1991-04-08 | 1997-03-18 | Haraszti; Tegze P. | High performance, fault tolerant orthogonal shuffle memory and method |
US5325402A (en) | 1991-04-30 | 1994-06-28 | Nec Corporation | Method and arrangement for estimating data sequences transmsitted using Viterbi algorithm |
US5278703A (en) | 1991-06-21 | 1994-01-11 | Digital Equipment Corp. | Embedded servo banded format for magnetic disks for use with a data processing system |
EP0522578A2 (en) | 1991-07-12 | 1993-01-13 | Pioneer Electronic Corporation | Noise removing circuit |
US5392299A (en) | 1992-01-15 | 1995-02-21 | E-Systems, Inc. | Triple orthogonally interleaed error correction system |
US5513192A (en) | 1992-08-28 | 1996-04-30 | Sun Microsystems, Inc. | Fault tolerant disk drive system with error detection and correction |
EP0631277A3 (en) | 1993-06-22 | 1995-02-22 | Quantum Corp | ID-less data sector format and data controller for disk drive. |
US5710784A (en) | 1993-09-24 | 1998-01-20 | Qualcomm Incorporated | Multirate serial viterbi decoder for code division multiple access system applications |
US5768044A (en) | 1993-12-23 | 1998-06-16 | International Business Machines Corporation | Zoned recording embedded servo disk drive having no data identification fields and reduced rotational latency |
US5523903A (en) | 1993-12-23 | 1996-06-04 | International Business Machines Corporation | Sector architecture for fixed block disk drive |
US5550870A (en) | 1994-03-02 | 1996-08-27 | Lucent Technologies Inc. | Viterbi processor |
US6041432A (en) | 1994-03-04 | 2000-03-21 | Sony Corporation | Apparatus and method for detecting signal points using signal point-mapping |
US5717706A (en) | 1994-03-04 | 1998-02-10 | Sony Corporation | Apparatus and method for detecting signal points using signal point-mapping |
US5471500A (en) | 1994-03-08 | 1995-11-28 | At&T Ipm Corp. | Soft symbol decoding |
US5844945A (en) | 1994-04-12 | 1998-12-01 | Goldstar Co., Ltd. | Viterbi decoder for a high definition television |
US5712861A (en) | 1994-07-12 | 1998-01-27 | Mitsubishi Denki Kabushiki Kaisha | Error correcting method and decoder with improved reliability |
US5898710A (en) | 1995-06-06 | 1999-04-27 | Globespan Technologies, Inc. | Implied interleaving, a family of systematic interleavers and deinterleavers |
US5701314A (en) | 1995-12-21 | 1997-12-23 | Cirrus Logic, Inc. | On-the-fly error correction using thermal asperity erasure pointers from a sampled amplitude read channel in a magnetic disk drive |
US5923713A (en) | 1996-02-28 | 1999-07-13 | Sony Corporation | Viterbi decoder |
US6023783A (en) | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
US5978414A (en) | 1996-07-03 | 1999-11-02 | Matsushita Electric Industrial Co., Ltd. | Transmission rate judging unit |
US6476989B1 (en) | 1996-07-09 | 2002-11-05 | International Business Machines Corporation | Radial self-propagation pattern generation for disk file servowriting |
US5802118A (en) | 1996-07-29 | 1998-09-01 | Cirrus Logic, Inc. | Sub-sampled discrete time read channel for computer storage systems |
US6065149A (en) | 1996-11-21 | 2000-05-16 | Matsushita Electric Industrial Co., Ltd. | Error correction device for a communication system |
US5983383A (en) | 1997-01-17 | 1999-11-09 | Qualcom Incorporated | Method and apparatus for transmitting and receiving concatenated code data |
US6671404B1 (en) | 1997-02-14 | 2003-12-30 | Hewlett-Packard Development Company, L.P. | Method and apparatus for recognizing patterns |
US6377610B1 (en) | 1997-04-25 | 2002-04-23 | Deutsche Telekom Ag | Decoding method and decoding device for a CDMA transmission system for demodulating a received signal available in serial code concatenation |
US6029264A (en) | 1997-04-28 | 2000-02-22 | The Trustees Of Princeton University | System and method for error correcting a received data stream in a concatenated system |
US6317472B1 (en) | 1997-08-07 | 2001-11-13 | Samsung Electronics Co., Ltd. | Viterbi decoder |
US6005897A (en) | 1997-12-16 | 1999-12-21 | Mccallister; Ronald D. | Data communication system and method therefor |
US6097764A (en) | 1997-12-16 | 2000-08-01 | Sicom, Inc. | Pragmatic trellis-coded modulation system and method therefor |
US6748034B2 (en) | 1997-12-19 | 2004-06-08 | Sony Corporation | Viterbi decoding apparatus and viterbi decoding method |
US6788654B1 (en) | 1998-01-29 | 2004-09-07 | Nippon Hoso Kyokai | Digital data receiver |
US6145110A (en) | 1998-06-22 | 2000-11-07 | Ericsson Inc. | Digital data decoder that derives codeword estimates from soft data |
US6366624B1 (en) * | 1998-11-30 | 2002-04-02 | Ericsson Inc. | Systems and methods for receiving a modulated signal containing encoded and unencoded bits using multi-pass demodulation |
US6625775B1 (en) | 1998-12-10 | 2003-09-23 | Samsung Electronics Co., Ltd. | Encoder/decoder with serial concatenated structure in communication system |
US6381726B1 (en) | 1999-01-04 | 2002-04-30 | Maxtor Corporation | Architecture for soft decision decoding of linear block error correcting codes |
US6216249B1 (en) | 1999-03-03 | 2001-04-10 | Cirrus Logic, Inc. | Simplified branch metric for reducing the cost of a trellis sequence detector in a sampled amplitude read channel |
US6216251B1 (en) | 1999-04-30 | 2001-04-10 | Motorola Inc | On-chip error detection and correction system for an embedded non-volatile memory array and method of operation |
US6438717B1 (en) | 1999-05-26 | 2002-08-20 | 3Com Corporation | High speed parallel bit error rate tester |
US6266795B1 (en) | 1999-05-28 | 2001-07-24 | Lucent Technologies Inc. | Turbo code termination |
US6351832B1 (en) | 1999-05-28 | 2002-02-26 | Lucent Technologies Inc. | Turbo code symbol interleaver |
US6473878B1 (en) | 1999-05-28 | 2002-10-29 | Lucent Technologies Inc. | Serial-concatenated turbo codes |
US6229467B1 (en) | 1999-05-28 | 2001-05-08 | Telefonaktiebolaget Lm Ericsson (Publ) | Correction static errors in a/d-converter |
US6657803B1 (en) | 1999-11-22 | 2003-12-02 | Seagate Technology Llc | Method and apparatus for data error recovery using defect threshold detector and viterbi gain |
US7310768B2 (en) | 2000-01-28 | 2007-12-18 | Conexant Systems, Inc. | Iterative decoder employing multiple external code error checks to lower the error floor |
US6810502B2 (en) | 2000-01-28 | 2004-10-26 | Conexant Systems, Inc. | Iteractive decoder employing multiple external code error checks to lower the error floor |
US7010051B2 (en) | 2000-03-24 | 2006-03-07 | Sony Corporation | Coding apparatus, coding method and recording medium having coded program recorded therein, and decoding apparatus, decoding method and recording medium having decoded program recorded therein |
US7184486B1 (en) | 2000-04-27 | 2007-02-27 | Marvell International Ltd. | LDPC encoder and decoder and method thereof |
US6757862B1 (en) | 2000-08-21 | 2004-06-29 | Handspring, Inc. | Method and apparatus for digital data error correction coding |
US7502189B2 (en) | 2000-10-23 | 2009-03-10 | Hitachi Global Storage Technologies Japan, Ltd. | Apparatus, signal-processing circuit and device for magnetic recording system |
US7093179B2 (en) | 2001-03-22 | 2006-08-15 | University Of Florida | Method and coding means for error-correction utilizing concatenated parity and turbo codes |
US20030134607A1 (en) | 2001-07-11 | 2003-07-17 | Raghavan Sreeen A. | Multi-channel communications transceiver |
US20030087634A1 (en) | 2001-07-11 | 2003-05-08 | Raghavan Sreen A. | 10165368High-speed multi-channel communications transceiver with inter-channel interference filter |
US20100002795A1 (en) | 2001-07-11 | 2010-01-07 | Entropic Communications, Inc. | Low Complexity High-Speed Communications Transceiver |
US7590168B2 (en) | 2001-07-11 | 2009-09-15 | Entropic Communications, Inc. | Low complexity high-speed communications transceiver |
US7403752B2 (en) | 2001-07-11 | 2008-07-22 | Vativ Technologies, Inc. | Multi-channel communications transceiver |
US20030112896A1 (en) | 2001-07-11 | 2003-06-19 | Raghavan Sreen A. | Multi-channel communications transceiver |
US7236757B2 (en) | 2001-07-11 | 2007-06-26 | Vativ Technologies, Inc. | High-speed multi-channel communications transceiver with inter-channel interference filter |
US20030081693A1 (en) | 2001-07-11 | 2003-05-01 | Raghavan Sreen A. | Low complexity high-speed communications transceiver |
US20070286270A1 (en) | 2001-09-05 | 2007-12-13 | Mediatek Inc. | Read channel apparatus and method for an optical storage system |
US7073118B2 (en) | 2001-09-17 | 2006-07-04 | Digeo, Inc. | Apparatus and method for saturating decoder values |
US7173783B1 (en) | 2001-09-21 | 2007-02-06 | Maxtor Corporation | Media noise optimized detector for magnetic recording |
US20030063405A1 (en) | 2001-10-02 | 2003-04-03 | Ming Jin | Method and apparatus for detecting media defects |
US6980382B2 (en) | 2001-11-09 | 2005-12-27 | Fujitsu Limited | Magnetic disk drive system |
US6986098B2 (en) | 2001-11-20 | 2006-01-10 | Lsi Logic Corporation | Method of reducing miscorrections in a post-processor using column parity checks |
US20050111540A1 (en) | 2001-11-21 | 2005-05-26 | David Modrie | Adaptive equalizer operating at a sampling rate asynchronous to the data rate |
US7136244B1 (en) | 2002-02-22 | 2006-11-14 | Western Digital Technologies, Inc. | Disk drive employing data averaging techniques during retry operations to facilitate data recovery |
US7203887B2 (en) | 2002-07-03 | 2007-04-10 | The Directtv Group, Inc. | Method and system for routing in low density parity check (LDPC) decoders |
US7191378B2 (en) | 2002-07-03 | 2007-03-13 | The Directv Group, Inc. | Method and system for providing low density parity check (LDPC) encoding |
US20040071206A1 (en) | 2002-08-13 | 2004-04-15 | Fujitsu Limited. | Digital filter adaptively learning filter coefficient |
US7113356B1 (en) | 2002-09-10 | 2006-09-26 | Marvell International Ltd. | Method for checking the quality of servo gray codes |
US6785863B2 (en) | 2002-09-18 | 2004-08-31 | Motorola, Inc. | Method and apparatus for generating parity-check bits from a symbol set |
US7058873B2 (en) | 2002-11-07 | 2006-06-06 | Carnegie Mellon University | Encoding method using a low density parity check code with a column weight of two |
US20040098659A1 (en) | 2002-11-18 | 2004-05-20 | Bjerke Bjorn A. | Rate-compatible LDPC codes |
US7047474B2 (en) | 2002-12-23 | 2006-05-16 | Do-Jun Rhee | Decoding concatenated codes via parity bit recycling |
US7505537B1 (en) | 2003-03-25 | 2009-03-17 | Marvell International Ltd. | System and method for controlling gain and timing phase in a presence of a first least mean square filter using a second adaptive filter |
US20050010855A1 (en) | 2003-07-09 | 2005-01-13 | Itay Lusky | Reduced complexity decoding for trellis coded modulation |
US7203015B2 (en) | 2003-07-31 | 2007-04-10 | Kabushiki Kaisha Toshiba | Method and apparatus for decoding sync marks in a disk |
US7313750B1 (en) | 2003-08-06 | 2007-12-25 | Ralink Technology, Inc. | Efficient soft decision demapper to minimize viterbi decoder complexity |
US7430256B2 (en) | 2003-09-26 | 2008-09-30 | Samsung Electronics Co., Ltd. | Method and apparatus for providing channel state information |
US20050078399A1 (en) | 2003-10-10 | 2005-04-14 | Seagate Technology Llc | Using data compression to achieve lower linear bit densities on a storage medium |
US7257764B2 (en) | 2003-11-03 | 2007-08-14 | Broadcom Corporation | FEC (Forward Error Correction) decoder with dynamic parameters |
US20050157780A1 (en) | 2003-12-17 | 2005-07-21 | Werner Carl W. | Signaling system with selectively-inhibited adaptive equalization |
US20060031737A1 (en) | 2004-02-19 | 2006-02-09 | Trellisware Technologies, Inc. | Method and apparatus for communications using improved turbo like codes |
US20050216819A1 (en) | 2004-02-19 | 2005-09-29 | Trellisware Technologies, Inc. | Method and apparatus for communications using turbo like codes |
US20050195749A1 (en) | 2004-03-05 | 2005-09-08 | Elmasry George F. | Method and system for capacity analysis for On The Move adhoc wireless packet-switched networks |
US20050273688A1 (en) | 2004-06-02 | 2005-12-08 | Cenk Argon | Data communication system with multi-dimensional error-correction product codes |
US20060020872A1 (en) | 2004-07-21 | 2006-01-26 | Tom Richardson | LDPC encoding methods and apparatus |
US20090259915A1 (en) | 2004-10-12 | 2009-10-15 | Michael Livshitz | Structured low-density parity-check (ldpc) code |
US20060123285A1 (en) | 2004-11-16 | 2006-06-08 | De Araujo Daniel F | Dynamic threshold scaling in a communication system |
US20060140311A1 (en) | 2004-12-23 | 2006-06-29 | Agere Systems Inc. | Composite data detector and a method for detecting data |
US20060168493A1 (en) | 2005-01-24 | 2006-07-27 | Agere Systems Inc. | Data detection and decoding system and method |
US20060195772A1 (en) | 2005-02-28 | 2006-08-31 | Nils Graef | Method and apparatus for evaluating performance of a read channel |
US20060210002A1 (en) | 2005-03-03 | 2006-09-21 | Xueshi Yang | Timing recovery in a parallel channel communication system |
US7370258B2 (en) | 2005-04-28 | 2008-05-06 | Sandbridge Technologies Inc. | Iterative concatenated convolutional Reed-Solomon decoding method |
US20060248435A1 (en) | 2005-04-29 | 2006-11-02 | Haratsch Erich F | Method and apparatus for iterative error-erasure decoding |
US7587657B2 (en) | 2005-04-29 | 2009-09-08 | Agere Systems Inc. | Method and apparatus for iterative error-erasure decoding |
US20060256670A1 (en) | 2005-05-16 | 2006-11-16 | Samsung Electronics Co., Ltd. | Signal-to-noise ratio measurement apparatus and method for signal read out of optical disc |
US20070011569A1 (en) | 2005-06-20 | 2007-01-11 | The Regents Of The University Of California | Variable-rate low-density parity check codes with constant blocklength |
US20070047635A1 (en) | 2005-08-24 | 2007-03-01 | Stojanovic Vladimir M | Signaling system with data correlation detection |
US20070047121A1 (en) | 2005-08-26 | 2007-03-01 | Eleftheriou Evangelos S | Read channel apparatus for asynchronous sampling and synchronous equalization |
EP1814108B1 (en) | 2005-09-12 | 2008-11-26 | Sony Corporation | Noise reducing apparatus, method and program and sound pickup apparatus for electronic equipment |
US7523375B2 (en) | 2005-09-21 | 2009-04-21 | Distribution Control Systems | Set of irregular LDPC codes with random structure and low encoding complexity |
US20070110200A1 (en) | 2005-11-15 | 2007-05-17 | Gokhan Mergen | Equalizer for a receiver in a wireless communication system |
US7509927B2 (en) | 2006-01-25 | 2009-03-31 | Comfort-Sinusverteiler Gmbh | Hydraulic header for a heating system |
US7712008B2 (en) | 2006-01-26 | 2010-05-04 | Agere Systems Inc. | Systems and methods for error reduction associated with information transfer |
US7752523B1 (en) | 2006-02-13 | 2010-07-06 | Marvell International Ltd. | Reduced-complexity decoding of parity check codes |
US20070230407A1 (en) | 2006-03-31 | 2007-10-04 | Petrie Michael C | Dynamic, adaptive power control for a half-duplex wireless communication system |
US20080065970A1 (en) | 2006-07-31 | 2008-03-13 | Agere Systems Inc. | Systems and Methods for Code Dependency Reduction |
US7801200B2 (en) | 2006-07-31 | 2010-09-21 | Agere Systems Inc. | Systems and methods for code dependency reduction |
US20080055122A1 (en) | 2006-07-31 | 2008-03-06 | Agere Systems Inc. | Systems and Methods for Code Based Error Reduction |
US7802163B2 (en) | 2006-07-31 | 2010-09-21 | Agere Systems Inc. | Systems and methods for code based error reduction |
US7738201B2 (en) | 2006-08-18 | 2010-06-15 | Seagate Technology Llc | Read error recovery using soft information |
US20080049825A1 (en) | 2006-08-25 | 2008-02-28 | Broadcom Corporation | Equalizer with reorder |
US20080069373A1 (en) | 2006-09-20 | 2008-03-20 | Broadcom Corporation | Low frequency noise reduction circuit architecture for communications applications |
US7702989B2 (en) | 2006-09-27 | 2010-04-20 | Agere Systems Inc. | Systems and methods for generating erasure flags |
US20100050043A1 (en) | 2006-12-01 | 2010-02-25 | Commissariat A L'energie Atomique | Method and device for decoding ldpc codes and communication apparatus including such device |
US20080168330A1 (en) | 2007-01-08 | 2008-07-10 | Agere Systems Inc. | Systems and methods for prioritizing error correction data |
US20080276156A1 (en) | 2007-05-01 | 2008-11-06 | Texas A&M University System | Low density parity check decoder for regular ldpc codes |
US20080301521A1 (en) | 2007-05-01 | 2008-12-04 | Texas A&M University System | Low density parity check decoder for irregular ldpc codes |
US20100185914A1 (en) | 2007-09-28 | 2010-07-22 | Weijun Tan | Systems and Methods for Reduced Complexity Data Processing |
US20100042877A1 (en) | 2007-10-01 | 2010-02-18 | Weijun Tan | Systems and Methods for Media Defect Detection |
US20090185643A1 (en) | 2008-01-22 | 2009-07-23 | Fitzpatrick Kelly K | Methods and Apparatus for Map Detection with Reduced Complexity |
US20090199071A1 (en) | 2008-02-05 | 2009-08-06 | Agere Systems Inc. | Systems and Methods for Low Cost LDPC Decoding |
US20090235116A1 (en) | 2008-03-17 | 2009-09-17 | Agere Systems Inc. | Systems and Methods for Regenerating Data from a Defective Medium |
US20090235146A1 (en) | 2008-03-17 | 2009-09-17 | Agere Systems Inc. | Systems and Methods for Using Intrinsic Data for Regenerating Data from a Defective Medium |
US20110075569A1 (en) | 2008-04-18 | 2011-03-31 | Link_A_Media Devices Corporation | Obtaining parameters for minimizing an error event probability |
US20090274247A1 (en) | 2008-04-30 | 2009-11-05 | Richard Leo Galbraith | Detection of synchronization mark from output of matched filter upstream of viterbi detector |
US20090273492A1 (en) | 2008-05-02 | 2009-11-05 | Lsi Corporation | Systems and Methods for Queue Based Data Detection and Decoding |
US20100164764A1 (en) | 2008-05-19 | 2010-07-01 | Ratnakar Aravind Nayak | Systems and Methods for Mitigating Latency in a Data Detector Feedback Loop |
US20100042890A1 (en) | 2008-08-15 | 2010-02-18 | Lsi Corporation | Error-floor mitigation of ldpc codes using targeted bit adjustments |
US20100061492A1 (en) | 2008-09-05 | 2010-03-11 | Lsi Corporation | Reduced Frequency Data Processing Using a Matched Filter Set Front End |
US20100070837A1 (en) | 2008-09-17 | 2010-03-18 | LSI Corporatrion | Power Reduced Queue Based Data Detection and Decoding Systems and Methods for Using Such |
US20110080211A1 (en) | 2008-11-20 | 2011-04-07 | Shaohua Yang | Systems and Methods for Noise Reduced Data Detection |
WO2010101578A1 (en) | 2009-03-05 | 2010-09-10 | Lsi Corporation | Improved turbo-equalization methods for iterative decoders |
US20110167246A1 (en) | 2010-01-04 | 2011-07-07 | Lsi Corporation | Systems and Methods for Data Detection Including Dynamic Scaling |
Non-Patent Citations (91)
Title |
---|
Amer et al "Design Issues for a Shingled Write Disk System" MSST IEEE 26th Symposium May 2010. |
Bahl, et al "Optimal decoding of linear codes for Minimizing symbol error rate", IEEE Trans. Inform. Theory, vol. 20, pp. 284-287, Mar. 1974. |
Casado et al., Multiple-rate low-denstiy parity-check codes with constant blocklength, IEEE Transations on communications, Jan. 2009, vol. 57, pp. 75-83. |
Collins and Hizlan, "Determinate State Convolutional Codes" IEEE Transactions on Communications, Dec. 1993. |
Eleftheriou, E. et al., "Low Density Parity-Check Codes for Digital Subscriber Lines", Proc ICC 2002, pp. 1752-1757. |
Fisher, R et al., "Adaptive Thresholding"[online] 2003 [retrieved on May 28, 2010] Retrieved from the Internet <URL:http://homepages.inf.ed.ac.uk/rbf/HIPR2/adpthrsh.htm. |
Fossnorier, Marc P.C. "Quasi-Cyclic Low-Density Parity-Check Codes From Circulant Permutation Maricies" IEEE Transactions on Information Theory, vol. 50, No. 8 Aug. 8, 2004. |
Gibson et al "Directions for Shingled-Write and Two-Dimensional Magnetic Recording System" Architectures: Synergies with Solid-State Disks Carnegie Mellon Univ. May 1, 2009. |
Hagenauer, J. et al A Viterbi Algorithm with Soft-Decision Outputs and its Applications in Proc. IEEE Globecom, pp. 47. 11-47 Dallas, TX Nov. 1989. |
Han and Ryan, "Pinning Techniques for Low-Floor Detection/Decoding of LDPC-Coded Partial Response Channels", 5th International Symposium on Turbo Codes &Related Topics, 2008. |
K. Gunnam "Area and Energy Efficient VLSI Architectures for Low-Density Parity-Check Decoders Using an On-The-Fly Computation" dissertation at Texas A&M University, Dec. 2006. |
K. Gunnam et al., "Next Generation iterative LDPC solutions for magnetic recording storage", invited paper. The Asilomar Conference on Signals, Systems, and Computers, Nov. 2008. |
K. Gunnam et al., "Value-Reuse Properties of Min-Sum for GF(q)" (dated Oct. 2006) Dept. of ECE, Texas A&M University Technical Note, published about Aug. 2010. |
K. Gunnam et al., "Value-Reuse Properties of Min-Sum for GF(q)"(dated Jul. 2008) Dept. of ECE, Texas A&M University Technical Note, published about Aug. 2010. |
Lee et al., "Partial Zero-Forcing Adaptive MMSE Receiver for DS-CDMA Uplink in Multicell Environments" IEEE Transactions on Vehicular Tech. vol. 51, No. 5, Sep. 2002. |
Lin et al "An efficient VLSI Architecture for non binary LDPC decoders"-IEEE Transaction on Circuits and Systems II vol. 57, Issue 1 (Jan. 2010) pp. 51-55. |
Mohsenin et al., "Split Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture", pp. 1-6, printed from www.ece.ucdavis.edu on Jul. 9, 2007. |
Moon et al, "Pattern-dependent noise prediction in signal-dependent Noise," IEEE JSAC, vol. 19, No. 4 pp. 730-743, Apr. 2001. |
Perisa et al "Frequency Offset Estimation Based on Phase Offsets Between Sample Correlations" Dept. of Info. Tech. University of Ulm 2005. |
Sari H et al., "Transmission Techniques for Digital Terrestrial TV Broadcasting" IEEE Communications Magazine, IEEE Service Center NY, NY vol. 33, No. 2 Feb. 1995. |
Selvarathinam, A.: "Low Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels" IEEE International Conference on Computer Design (ICCD '03) 2003. |
Shu Lin, Ryan, "Channel Codes, Classical and Modern" 2009, Cambridge University Press, pp. 213-222. |
U.S. Appl. No. 11/461,026, filed Jul. 31, 2006, Tan, Weijun. |
U.S. Appl. No. 11/461,198, filed Jul. 31, 2006, Tan, Weijun. |
U.S. Appl. No. 11/461,283, filed Jul. 31, 2006, Tan, Weijun. |
U.S. Appl. No. 12/540,283, filed Aug. 12, 2009, Liu, et al. |
U.S. Appl. No. 12/652,201, filed Jan. 5, 2010, Mathew, et al. |
U.S. Appl. No. 12/763,050, filed Apr. 19, 2010, Ivkovic, et al. |
U.S. Appl. No. 12/792,555, filed Jun. 2, 2010, Liu, et al. |
U.S. Appl. No. 12/887,317, filed Sep. 21, 2010, Xia, et al. |
U.S. Appl. No. 12/887,330, filed Sep. 21, 2010, Zhang, et al. |
U.S. Appl. No. 12/887,369, filed Sep. 21, 2010, Liu, et al. |
U.S. Appl. No. 12/901,742, filed Oct. 11, 2010, Yang. |
U.S. Appl. No. 12/901,816, filed Oct. 11, 2010, Li, et al. |
U.S. Appl. No. 12/917,756, filed Nov. 2, 2010, Miladinovic, et al. |
U.S. Appl. No. 12/947,931, filed Nov. 17, 2010, Yang, Shaohua. |
U.S. Appl. No. 12/947,947, filed Nov. 17, 2010, Ivkovic, et al. |
U.S. Appl. No. 12/972,942, filed Dec. 20, 2010, Liao, et al. |
U.S. Appl. No. 12/992,948, filed Nov. 16, 2010, Yang, et al. |
U.S. Appl. No. 13/021,814, filed Feb. 7, 2011, Jin, Ming, et al. |
U.S. Appl. No. 13/031,818, filed Feb. 22, 2011, Xu, Changyou, et al. |
U.S. Appl. No. 13/050,129, filed Mar. 17, 2011, Tan, et al. |
U.S. Appl. No. 13/050,765, filed Mar. 17, 2011, Yang, et al. |
U.S. Appl. No. 13/088,119, filed Apr. 15, 2011, Zhang, et al. |
U.S. Appl. No. 13/088,146, filed Apr. 15, 2011, Li, et al. |
U.S. Appl. No. 13/088,178, filed Apr. 15, 2011, Sun, et al. |
U.S. Appl. No. 13/126,748, filed Apr. 28, 2011, Tan. |
U.S. Appl. No. 13/167,764, filed Jun. 24, 2011, Li, Zongwang, et al. |
U.S. Appl. No. 13/167,771, filed Jun. 24, 2011, Li, Zongwang, et al. |
U.S. Appl. No. 13/167,775, filed Jun. 24, 2011, Li, Zongwang. |
U.S. Appl. No. 13/186,146, filed Jul. 19, 2011, Mathew, et al. |
U.S. Appl. No. 13/186,174, filed Jul. 19, 2011, Mathew, et al. |
U.S. Appl. No. 13/186,197, filed Jul. 19, 2011, Mathew, George et al. |
U.S. Appl. No. 13/186,213, filed Jul. 19, 2011, Mathew, et al. |
U.S. Appl. No. 13/186,234, filed Jul. 19, 2011, Xia, Haitao, et al. |
U.S. Appl. No. 13/186,251, filed Jul. 19, 2011, Xia, Haitao, et al. |
U.S. Appl. No. 13/213,751, filed Aug. 19, 2011, Zhang, Fan, et al. |
U.S. Appl. No. 13/213,808, filed Aug. 19, 2011, Jin, Ming. |
U.S. Appl. No. 13/220,142, filed Aug. 29, 2011, Chang, Wu, et al. |
U.S. Appl. No. 13/227,538, filed Sep. 8, 2011, Yang, Shaohua, et al. |
U.S. Appl. No. 13/227,544, filed Sep. 8, 2011, Yang, Shaohua, et al. |
U.S. Appl. No. 13/239,683, filed Sep. 22, 2011, Xu, Changyou. |
U.S. Appl. No. 13/239,719, filed Sep. 22, 2011, Xia, Haitao, et al. |
U.S. Appl. No. 13/251,340, filed Oct. 3, 2011, Xia, Haitao, et al. |
U.S. Appl. No. 13/251,342, filed Oct. 2, 2011, Xia, Haitao, et al. |
U.S. Appl. No. 13/269,832, filed Oct. 10, 2011, Xia, Haitao, et al. |
U.S. Appl. No. 13/269,852, filed Oct. 10, 2011, Xia, Haitao, et al. |
U.S. Appl. No. 13/284,730, filed Oct. 28, 2011, Zhang, Fan, et al. |
U.S. Appl. No. 13/284,754, filed Oct. 28, 2011, Zhang, Fan, et al. |
U.S. Appl. No. 13/284,767, filed Oct. 28, 2011, Zhang, Fan, et al. |
U.S. Appl. No. 13/284,819, filed Oct. 28, 2011, Tan, Weijun, et al. |
U.S. Appl. No. 13/284,826, filed Oct. 28, 2011, Tan, Weijun, et al. |
U.S. Appl. No. 13/295,150, filed Nov. 14, 2011, Li, Zongwang, et al. |
U.S. Appl. No. 13/295,160, filed Nov. 14, 2011, Li, Zongwang, et al. |
Unknown, "Auto threshold and Auto Local Threshold" [online] [retrieved May 28, 2010] Retrieved from the Internet: <URL:http://www.dentristy.bham.ac.uk/landinig/software/autoth. |
Vasic, B., "High-Rate Girth-Eight Codes on Rectangular Integer Lattices", IEEE Trans. Communications, vol. 52, Aug. 2004, pp. 1248-1252. |
Vasic, B., "High-Rate Low-Density Parity-Check Codes Based on Anti-Pasch Affine Geometries," Proc ICC 2002, pp. 1332-1336. |
Wang Y et al., "A Soft Decision Decoding Scheme for Wireless COFDM With Application to DVB-T" IEEE Trans. on Consumer elec., IEEE Service Center, NY,NY vo. 50, No. 1 Feb. 2004. |
Weon-Cheol Lee et al., "Vitierbi Decoding Method Using Channel State Info. in COFDM System" IEEE Trans. on Consumer Elect., IEEE Service Center, NY, NY vol. 45, No. 3 Aug. 1999. |
Xia et al, "A Chase-GMD algorithm of Reed-Solomon codes on perpendicular channels", IEEE Transactions on Magnetics, vol. 42 pp. 2603-2605, Oct. 2006. |
Xia et al, "Reliability-based Reed-Solomon decoding for magnetic recording channels", IEEE International Conference on Communication pp. 1977-1981, May 2008. |
Yeo et al., "VLSI Architecture for Iterative Decoders in Magnetic Storage Channels", Mar. 2001, pp. 748-755, IEEE trans. Magnetics, vol. 37, No. 2. |
Youn, et al. "BER Perform. Due to Irrreg. of Row-Weight Distrib. of the Parity-Chk. Matirx in Irreg. LDPC Codes for 10-Gb/s Opt. Signls" Jrnl of Lightwave Tech., vol. 23, Sep. 2005. |
Zhong et al., "Area-Efficient Min-Sum Decoder VLSI Architecture for High-Rate QC-LDPC Codes in Magnetic Recording", pp. 1-15, Submitted 2006, not yet published. |
Zhong et al., "Design of VLSI Implementation-Oriented LDPC Codes", IEEE, pp. 670-673, 2003. |
Zhong et al., "High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel with Low Error Floor", ISCAS, IEEE pp. 3546-3549, May 2006. |
Zhong et al., "Iterative MAX-LOG-MAP and LDPC Detector/Decoder Hardware Implementation for Magnetic Read Channel", SRC TECHRON, pp. 1-4, Oct. 2005. |
Zhong et al., "Joint Code-Encoder Design for LDPC Coding System VLSI Implementation", ISCAS, IEEE pp. 389-392, May 2004. |
Zhong et al., "Quasi Cyclic Ldpc Codes for the Magnetic Recording Channel: Code Design and VSLI Implementation", IEEE Transactions on Magnetics, v. 43, pp. 1118-1123, Mar. 2007. |
Zhong, "Block-LDPC: A Practical LDPC Coding System Design Approach", IEEE Trans. on Circuits, Regular Papers, vol. 5, No. 4, pp. 766-775, Apr. 2005. |
Zhong, "VLSI Architecture of LDPC Based Signal Detection and Coding System for Magnetic Recording Channel", Thesis, RPI, Troy, NY, pp. 1-95, May 2006. |
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