WO2000034846A3 - Method, system, and computer program product for error detection and correction in a synchronization word - Google Patents

Method, system, and computer program product for error detection and correction in a synchronization word Download PDF

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Publication number
WO2000034846A3
WO2000034846A3 PCT/US1999/029445 US9929445W WO0034846A3 WO 2000034846 A3 WO2000034846 A3 WO 2000034846A3 US 9929445 W US9929445 W US 9929445W WO 0034846 A3 WO0034846 A3 WO 0034846A3
Authority
WO
WIPO (PCT)
Prior art keywords
synch word
synch
word
hamming distance
value
Prior art date
Application number
PCT/US1999/029445
Other languages
French (fr)
Other versions
WO2000034846A9 (en
WO2000034846A2 (en
Inventor
Moe A Lwin
Sunghun Choi
Original Assignee
Advanced Wireless Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Wireless Technologies filed Critical Advanced Wireless Technologies
Priority to AU23585/00A priority Critical patent/AU2358500A/en
Publication of WO2000034846A2 publication Critical patent/WO2000034846A2/en
Publication of WO2000034846A3 publication Critical patent/WO2000034846A3/en
Publication of WO2000034846A9 publication Critical patent/WO2000034846A9/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045Arrangements at the receiver end
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045Arrangements at the receiver end
    • H04L1/0054Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042Detectors therefor, e.g. correlators, state machines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving MPEG packets from an IP network
    • H04N21/4382Demodulation or channel decoding, e.g. QPSK demodulation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056Systems characterized by the type of code used
    • H04L1/0057Block codes

Abstract

A method, system, and computer product (100) detects and corrects error in a synchronization (synch) word. At least one bit error in a synch word is detected and corrected prior to correcting bit errors in a frame. In one embodiment, bit errors in a synch word are detected by locating (110) a synch word in data. A first Hamming distance between the located synch word and a first synch word value is calculated (120). A second Hamming distance between the located synch word and a second synch word value is also calculated (130). Next, the calculated first and second Hamming distances are compared (140) to detect which of the first and second synch word values is the correct synch word value. In one example, the first and second Hamming distances represent counts of the number of bit errors between the located synch word and the first and second synch word values, respectively. The first and second synch word values are binary complements to maximize accuracy. Detected synch word error is corrected (170) by replacing the located synch word with the first synch word value (150) in the received frame when the first Hamming distance is less than or equal to the second Hamming distance. Otherwise, the located synch word is replaced with the second synch word value (160) when the first Hamming distance is greater than the second Hamming distance. In one example implementation, the present invention is included in a receiver including, but not limited to, a Digital Video Broadcast (DVB) receiver that receives data from a satellite or cable.
PCT/US1999/029445 1998-12-11 1999-12-13 Method, system, and computer program product for error detection and correction in a synchronization word WO2000034846A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU23585/00A AU2358500A (en) 1998-12-11 1999-12-13 Method, system, and computer program product for error detection and correction in a synchronization word

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20929298A 1998-12-11 1998-12-11
US09/209,292 1998-12-11

Publications (3)

Publication Number Publication Date
WO2000034846A2 WO2000034846A2 (en) 2000-06-15
WO2000034846A3 true WO2000034846A3 (en) 2000-11-23
WO2000034846A9 WO2000034846A9 (en) 2001-05-10

Family

ID=22778186

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/029445 WO2000034846A2 (en) 1998-12-11 1999-12-13 Method, system, and computer program product for error detection and correction in a synchronization word

Country Status (2)

Country Link
AU (1) AU2358500A (en)
WO (1) WO2000034846A2 (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646303A (en) * 1983-10-05 1987-02-24 Nippon Gakki Seizo Kabushiki Kaisha Data error detection and correction circuit
US5031218A (en) * 1988-03-30 1991-07-09 International Business Machines Corporation Redundant message processing and storage
US5309450A (en) * 1990-04-30 1994-05-03 Samsung Electronics Co., Ltd. Error correction coding method and apparatus for digital image information
US5856979A (en) * 1996-04-15 1999-01-05 Robert Bosch Gmbh Error-robust multiplex process with retransmission
US5889793A (en) * 1997-06-27 1999-03-30 Integrated Device Technology, Inc. Methods and apparatus for error correction
US5920439A (en) * 1997-02-21 1999-07-06 Storage Technology Corporation Method for determining longitudinal position on a magnetic tape having an embedded position count field
US5987630A (en) * 1996-11-12 1999-11-16 Fujitsu Limited Method of descrambling scrambled data using a scramble pattern and scramble pattern generator
US5999110A (en) * 1998-02-17 1999-12-07 International Business Machines Corporation Defect tolerant binary synchronization mark

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646303A (en) * 1983-10-05 1987-02-24 Nippon Gakki Seizo Kabushiki Kaisha Data error detection and correction circuit
US5031218A (en) * 1988-03-30 1991-07-09 International Business Machines Corporation Redundant message processing and storage
US5309450A (en) * 1990-04-30 1994-05-03 Samsung Electronics Co., Ltd. Error correction coding method and apparatus for digital image information
US5856979A (en) * 1996-04-15 1999-01-05 Robert Bosch Gmbh Error-robust multiplex process with retransmission
US5987630A (en) * 1996-11-12 1999-11-16 Fujitsu Limited Method of descrambling scrambled data using a scramble pattern and scramble pattern generator
US5920439A (en) * 1997-02-21 1999-07-06 Storage Technology Corporation Method for determining longitudinal position on a magnetic tape having an embedded position count field
US5889793A (en) * 1997-06-27 1999-03-30 Integrated Device Technology, Inc. Methods and apparatus for error correction
US5999110A (en) * 1998-02-17 1999-12-07 International Business Machines Corporation Defect tolerant binary synchronization mark

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
AL-SUBBAGH M. ET AL.: "Optimum patterns for frame alignment", IEEE, December 1988 (1988-12-01), pages 594 - 603 *
CASTILLO F. ET AL.: "A neural inspired associative memory", IEEE, 1991, pages 1753 - 1757 *
CHRISTOPHER L. ET AL.: "A fully integrated digital demodulation and forward error correction IC for digital satellite television", IEEE, February 1995 (1995-02-01), pages 281 - 284 *
HAMMONS JR.: "CRC-based techniques for combined burst synchronization and error detection in TDMA PCS systems", IEEE, 1996, pages 472 - 476 *
HESHAMI M. ET AL.: "A 250-MHz skewed-clock pipelined data buffer", IEEE, 1996, pages 376 - 383 *
MIYAZAWA S. ET AL.: "A BiCMOS PLL-based data separator circuit high stability and accuracy", IEEE, 1991, pages 116 - 121 *
SOBEY C.: "Probability of error for fault-tolerant byte synchronization detectors", IEEE, June 1996 (1996-06-01), pages 1528 - 1532 *

Also Published As

Publication number Publication date
WO2000034846A9 (en) 2001-05-10
WO2000034846A2 (en) 2000-06-15
AU2358500A (en) 2000-06-26

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